Advanced IC Design and Software Engineering Training

From Algorithm to RTL in Synthesizable Verilog Program Agenda (Subject to Change Without Notice)

Day 1 1 Opening Remark 2 RTL Design under From Algorithm to System Context

2.1 Design Flows: FPGA, ASIC & COT
2.2 Design Views in Y Chart: Algorithmic, Structural & Physical
2.3 Migrating from ASIC Flow to COT Flow: What Is It & How It Can Be Done?
2.3 Computation Models: Control-flow, Data-flow & Hybrid
2.4 Timing Models: Untimed Vs Timed (Cycle-based & Discrete Event)
2.5 Algorithm Design, Specification & Optimization in HLL: C, C++, Java & MatLab
2.6 Behavioral/ Transaction-level Design, Specification & Optimization in System-level Design Language: SystemC & SystemVerilog In Depth
2.7 HW/SW Co-design: Partitioning, Co-verification & Co-validation
2.8 EDA Flow Setup, Validation & Turning with Scripting Languages: Tcl & Perl In Depth
2.9 Verification & Validation for RTL Design ? Solutions to Verification Challenges
2.10 Bridging Logic Design to Physical Design ? Solutions to Timing Closure Challenges
2.11 On RTL Design Frontier: High Speed, Low Power Design 1 IP-based SoC Design Reuse: Never Reinvent Your Wheel 2 Verilog for HW Design ? Part I

3.1 Digital Design Strategies & Techniques
3.2 Verilog Syntax Basics
3.3 Hierarchical Modeling Concepts in Verilog
3.4 Behavioral Subset of Verilog
3.5 The Parameterized Design ? The 1st Step for Design Reuse 1 Verilog Coding Styles 2 Verilog for HW Design ? Part II

4.1 Structural Subset of Verilog
4.2 Useful Modeling Techniques in Verilog
4.3 Timing & Delays in Verilog
4.4 Verilog PLI 1 Verilog Test Fixtures 2 The Essence of RTL Design

5.1 Temporal Domain & Spatial Domain of HW
5.2 Scheduling, Resource Allocation and Binding
5.3 Controller & Datapath
5.4 Controller: Hardwired Vs. Programmable
5.5 FSM: Mealy Machine Vs. Moore Machine
5.6 Datapath: Regular Vs. Irregular
5.7 Build High Performance Datapath
5.8 Memory Architecture In Depth: On-chip Flash, ROM, DRAM, SDRAM & CAM 1 Bus Architecture In Depth: High Performance Vs Low Cost 2 RTL Design Using ASM

6.1 On the ASM Chart
6.2 ASM Notations
6.3 The Theory behind ASM
6.4 Scheduling, Resource Allocation & Binding
6.5 Advanced ASM Techniques
6.6 The Trade-off between Mealy Machine & Moore Machine
6.7 The Trade-off between Datapath & Controller
6.8 RTL design in the SoC Context - When You Have to Deal with 3rd-Party IP)
6.9 Mini-Case Study: Designing an SRA (Square Root Approximation) Block

Day 2 1. Hard-wired Controller based RTL Design with ASM for Speed & Cost
1.1 The Cycle-based Delay Model
1.2 Multi-cycle, Chaining and Pipelining
1.3 Latency Vs. Throughput
1.4 Pipelining, Currency & Superscalar 1 Architecture-level Trade-off between Speed & Cost 2 Advanced Verilog for RTL Design ? Part I

2.1 Data Representation: Issues on Floating to Fixed-Point Optimization
2.2 Combinatorial Building Blocks: MUX, Decoders, Encoders & Priority encoders
2.3 Clocked Building Blocks: Edge-based Design Vs Latch-based Design
2.4 Interconnection Structures: Bus-based Vs MUX-based
2.5 Arithmetic Building Blocks: Custom Vs Synthesis-based
2.6 Datapath Functions: Organization and types of comparators, counters and ALUs
2.7 Finite State Machines: State Encoding &State Minimization
2.8 Memory structures: Basics, synchronous and dual port RAM, LIFO and FIFO structures 1 Partitioning Issues 2 Verilog Design for HW Design ? Part III

3.1 Verilog Hierarchy
3.2 Built-In Logic Primitives
3.3 User-Defined Primitives (UDP)
3.4 Library Parameterized Modules (LPM)
3.5 Latches and Flipflops
3.6 Blocking and Non-blocking Assignments 1 Miscellaneous Verilog Modeling Tricks 2 Verilog for HW Design ? Part IV

4.1 Simulation View Vs Synthesis View
4.2 Synthesizable Subset of Verilog
4.3 Synthesizable Subset of Verilog
4.4 Verilog Synthesis Styles
4.5 RTL Coding Styles for Verilog
4.6 Design for Performance/Cost Trade-off 1 Design for Design Reuse 2 Real Life Digital Design Strategies and Techniques

5.1 Synchronous Logic Rules
5.2 Clock Strategies
5.3 Design for Test Issues 1 Area/Delay Optimization 2 Issues in Real Life Digital Design

6.1 Verilog Hierarchy Revisited
6.2 Tri-state Signals and Buses
6.3 Reset, Preset, Tri-state and Bi-directional Signals
6.4 Priority Encoders
6.5 Area/Speed Optimization in Synthesis
6.6 Trade-off between Operating Speed and Latency
6.7 Delays in FPGA Elements
6.8 Design Partitioning 1 Scalable and Parameterized Design 2 Programmable Controller based RTL Design with ASM for Speed & Cost

7.1 MCU, CPU & DSP
7.2 CISC, RISC, SuperScalar & VLIW
7.3 The Impact of ISA on Programmable Microarchitecture
7.4 The Demands of Programmable Microarchitecture on Compiler
7.5 Controller Design for Programmable Microarchitecture
7.5.1 The Design of Custom ISA
7.5.2 The Design of Sequencer
7.5.3 On Decoding Logic
7.5.4 The Design of Custom Datapath
7.5.5 Memory Architecture Issues 1 Bus Architecture Issues 2 Building Blocks in Real Life Digital Design

8.1 Decoders and Encoders
8.2 Registers and Latches
8.3 Adders and Sub tractors
8.4 Multipliers and Dividers
8.5 Counters and Simple Arithmetic Functions
8.6 Finite State Machines Revisited
8.7 Register Files
8.8 ROM, RAM 1 FIFO and UART 2 Advanced Verilog for RTL Design ? Part II

9.1 Simulation View Vs Synthesis View ? How to Deal with Mismatches?
9.2 Synthesizable Subset of Verilog
9.3 RTL Coding Styles for Verilog: Synthesizability & Reusability
9.4 Design for Performance/Cost Trade-off: Partitioning & Timing Budgeting Verilog Hierarchy Revisited
9.5 Specific Design Issues
9.5.1 On Dealing with Long Wires
9.5.2 Gated Clock Vs Clock Enable
9.5.3 On Glitch Elimination Vs Redundancy Removal
9.5.4 Asynchronous Design and Metastability
9.5.4.1 Asynchronous Design Basics
9.5.4.2 Metastability and Mean Time Between Failure (MTBF) Calculation
9.5.4.3 On Handling Asynchronicity
9.5.4.4 On Multi-clock domain interfacing
9.5.5 On Design-For-Testability (DFT)
9.5.6 On Clock-Tree-Synthesis (CTS)
9.6 Trade-off between Operating Speed and Latency
9.7 Scalable and Parameterized Design ? The 1st Step for IP-based SoC Design

10. Case Study: Design CISC (PDP-8 subset) & RISC (ARM subset) CPU Using ASM

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