Advanced Synthesizable VHDL at RTL in Depth Program Agenda (Subject to Change without Notice)
1st Day (9:00AM ~ 12:00AM)
1 Opening Remark
2 Behavioral Modeling in VHDL
2.1 How to structure a behavioral model
2.2 Structuring a process to respond to external events
2.3 Handling asynchronous or unpredictable inputs
2.4 Modeling external timing relationships & Checking timing constraints
2.5 Modeling memories
2.6 Modeling interfaces for inclusion in a test bench Bus-functional models
1 Processor models
2 Functional Modeling in VHDL
3.1 Subprograms, parameters, assigning signals
3.2 User defined packages
3.3 Users defined array types
3.4 Record types, selected names, aggregates, and arrays of records
3.5 Types, subtypes and overloading, conversion functions
3.6 Qualified expressions
3.7 Generics, string generics, array generics Configurations, binding and dependencies, generic and port maps
3. How VHDL Works
3.1 Signal assignments
3.2 Events and inertial delay
3.3 Deltas Drivers and resolution functions
3.4 Wait statements
3.5 Static elaboration, the network model
1 Dynamic elaboration, elaboration arrays and files in subprograms
2 Open Discussion
1st Day (1:00PM ~ 4:00PM)
1. Arithmetic Functions & Datapath Elements
1.1 Arithmetic Functions in Predefined Packages
1.2 Loaded-able and Enable-able Counters
1.3 Operator Overloading
1.4 Vector Direction
1.5 Functions Available in the Standard Packages
1.6 Adders and Subtractors
1 Multiplication, Division and Exponentiation
2 Hardwired Controller Working with Datapath -The Essence of RTL Design
1.1 Typical Finite State Machine Blocks
1.2 Finite State Machine Input and Outputs
1.3 Developing the Finite State Diagram
1.4 Creating a Type for Your States
1.5 Coding the Next States Conditioning Logic
1.6 Registering the Current State Vector
1.7 Coding the Output Conditioning Logic
1 Issues Related to Finite State Machine Design Technique
2 Case Study I: The Complete PCI Target State Machine Design in VHDL
2.1 Determine the Datappath
2.2 Determine the Control Algorithm
2.3 Defining the Black Box
2.4 Describe the States Using Enumerated Types
2.5 Code the Next State Conditioning Logic
2.6 Code the Current State Register
2.7 Code the Output Conditioning Logic
1 Integrate with the Datapath
2 Open Discussion
2nd Day (9:00AM ~ 12:00AM)
1. Synthesis Issues in VHDL Modeling
1.1 Appreciating the finer points of syntax directed translation
1.2 Incomplete assignment, Latches and Re-circulation
1.3 Asynchronous inputs to clocked process
1.4 Inference versus instantiation the limits of combinational, register and arithmetic optimization
1.5 Using hierarchy to control synthesis
1.6 Timing constrains, area constrains, and optimization options
1.7 Optimal one-hot decoding
1.8 Multiple clock edges and partitioning clock domains
1.9 Synthesis methodology for large designs
1.10 Advanced styles for Finite State machines
1 Using the standard packages
2 IP-based Reuse in VHDL
2.1 Language level re-use
2.2 Standard component re-use General re-use
2.3 Packaging IP for re-use
2.4 Documenting IP, including test cases
2.5 Impact of IP-based reuse on design flow planning
2.6 Impact of IP-based reuse on revision control, bug tracking, archiving
2.7 Writing reusable VHDL
2.8 RTL VHDL style for capturing IP
2.8.1 Hierarchy and partitioning
2.8.2 Isolating tool and technology dependencies
2.8.3 Readability and maintainability
2.8.4 Seeing generalizeable properties
2.8.5 Array attributes, cloning ranges, arrays of arrays, unconstrained arrays, others
2.8.6 Seeing regular structures and using loops and generate
1 Using generics to parameterize and structures
2 Open Discussion
2nd Day (1:00PM ~ 4:00PM)
1. Design for Verification with Assertions
1.1 Why use assertions in your designs?
1.2 Introduction to Properties
1.3 Property languages
1.3.1 Property Specification Language (PSL)
1.3.2 Sugar Language
1.4 Open Verification Library (OVL)
1 Using OVL in VHDL
2 VHDL Test Benches
2.1 The Verification Plan
2.2 Structure of a simple test bench
2.3 Structure of a complex test bench
2.4 Procedural stimulus generation
2.5 Reactive test benches
2.6 Files I/O; TEXTIO and 'C' Interfacing
2.7 Measuring delays
2.8 Monitoring internal signals
2.9 Generating random numbers
2.10 Collecting diagnostic data
2.11 Storing inputs/outputs in a buffer
2.12 Tagging data and Scoreboards
2.13 Coping with latency and Out-of-Order completion
2.14 Control files
1 Generic and parameterized testbenches
2 Open Discussion
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