System Modeling & Verification with C++/C Program Agenda (Subject to Change without Notice)
1st Day (9:00AM ~ 12:00AM)
1 Opening Remark
2 Key Verification Issues for ASIC/SoC Design
2.1 ASIC/SoC Verification Goals: Efficiency & Reusability
2.2 The Verification Challenges in ASIC/SoC Design
2.3 The Big Gaps among Algorithm-level, Transaction-level & RTL
1 Computation Model, Communication Model & Timing Model
2 C++ for HW Modeling & Verification - Part I
3.1 Why C++?
3.1.1 What C Lacks?
3.1.2 What Is C++? - Data Abstraction, OO Programming & Generic Programming
3.1.3 What C++ Differs from C?
3.2 Data Abstraction, Information Hiding & Polymorphism
3.2.1 Classes Vs Objects: Static Modeling Vs Dynamic Modeling
3.2.2 Operator Overloading
3.2.3 Inheritance
3.2.3.1 Public Inheritance, Private Inheritance & Multiple Inheritance
3.2.3.2 Virtual Function In Depth: Dynamic Binding Instead of Static Binding
3.2.4 Parameterized Design with Templates: Class Templates Vs Function Templates
3.2.5 Exception Handling
3.2.6 Class Hierarchies
3.3 The Standard Library Vs Custom Library
3.3.1 Static Library Vs Dynamic (Shared) Library
3.3.2 Standard Library Organization and Containers
3.3.2 Standard Containers
3.3.3 Strings & Streams in Standard Library
3.3.4 How to Construct Your Own Library to Leverage C++'s Extensibility
3.4 Memory Management in C++
3.4.1 Memory Allocation & Deletion
3.4.2 Constructors & Destructors: Default Vs Custom
3.4.3 Copy Constructors
3.4.3 Assign Operators
3.5 SW Engineering Adopting C++
3.5.1 Algorithm & Data Structures
3.5.2 Requirement Elicitation & Management
3.5.2 SW Architecture
3.5.3 OO Modeling & Design with UML in Brief
3.5.4 Unit Test, Integration Test, System Test, Regression Test & QoR Test
3.5.5 Performance Turning, Code Coverage & Memory Leakage Detection
3.5.6 Extreme Programming at Practice
3.5.6.1 Version Control & Bug Tracking
3.5.6.2 The Daily Build/Test/Release & Milestone-based Synchronize & Stabilize Process
1 Advices for C Programmers Who Want to Migrate to C++ without Pain
2 Open Discussion
1st Day (1:00PM ~ 4:00PM)
1 Case Study I: Build an In-house General Purpose Library in C++
2 C++ for HW Modeling & Verification - Part II
2.1 C++ Design Flow for HW Modeling
2.2 Bus Functional Model (BFM) Design
2.3 Modeling Memory-mapped I/O
2.4 Modeling interrupt-driven I/O
2.5 Performance Estimation with BFM
2.6 On HW/SW Synchronization
2.6 SW Simulation with Instruction Set Simulator (ISS)
1 On Integrating an BFM & an ISS
2 Open Discussion
2nd Day (9:00AM ~ 12:00AM)
1.1 Advanced SystemC In Depth
1. 2Computation Models Supported by SystemC
1.3 Classical Modeling in SystemC
1.4 Parameterized Modules
1.5Interface & Channel Design
1.6 Transaction-level Modeling
1.7 Communication Refinement
1.8 Testbenches, Tracing & Debugging
1 The Synthesizable Subet of SystemC Vs The Verification Subset of SystemC
2 Transaction Level Modeling In Depth
2.1 What Is Transaction Level & Why Transaction Level Modeling?
2.2 Communication View of Transaction Level Modeling - Time Accuracy
2.3 Computation View of Transaction Modeling -Cycle Accuracy
2.4 Transaction Modeling Methodology & Flows
1 Prepare to Refine from Transaction Level to RTL
2 Case Study II: Transaction Level Modeling a Cache Memory in C++ with Custom Library Augment
3. Open Discussion
2nd Day (1:00PM ~ 4:00PM)
1. Transaction Level Verification on Top of SystemC In Depth
1.1 Functional Simulation Vs Functional Code Coverage
1.2 Testbench Automation for Smart Verification: Deterministic Tests, Directed Random Tests & Trace-driven Tests
1.3. Concepts in Transaction-based Verification Environment: Transactions, Transaction Verification Models & Transaction-based Tests
1.4. The Layered Testbench Architecture
1.5 Data Introspection: Static Extension Vs Dynamic Extension
1.6 Randomization Issues: Weighted Vs Constrained
1.7 Constraints Creation & Handling: Soft Vs Hard; Flat Vs Hierarchical
1.8 Transaction Recording & Monitoring
1 A Detailed Analysis of SystemC's Verification Package
2 Tricks on Testbench Authoring& Design Debugging
2.1 Partition of Responsibility
2.2 Cause & Effect Testing
2.3 Complex Concurrency
1 Constrained Random Testing
2 Case Study III: Transaction Level Verification in a Million-Gate ASIC Verification Flow
3 Open Discussion
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