Automatice Testbench Generation in Verilog Program Agenda (Subject to Change without Notice)
1st Day
(9:00AM ~ 12:00AM)
1 Opening Remark
2 Functional Verification at a Glance
2.1 Functional Verification Approaches: Testing vs. Verification; Formal Vs Informal
2.2 The Functional Verification Plan
2.2.1 The Role of the Verification Plan
2.2.2 Abstraction Level of Verification
2.2.3 Verification Strategies
2.2.4 From Specification to Features
2.2.5 From Features to Test cases
2.2.6 From Test cases to Testbenches
2.3 Stimulus and Response
2.3.1 Self-Checking Testbenches
2.3.2 Complex Stimulus & Complex Response
2.3.3 Predicting the Output
2.4 Architecting Testbenches
2.4.1 Reusable Verification Components
2.4.2 Autonomous Generation and Monitoring. Input and Output Paths
2.4.3 Verifying Configurable Designs
2.5 Regression Test Revisited
2.5.1 The Golden Result Concept
2.5.2 The Version Control Systems & the Issue/Bug Tracking System
2.5.3 The Daily Build/Test/Release and Milestone-based Synchronize & Stabilize Practice
1 On Automatic Test Bench Generation with Guaranteed Coverage
2 Analyzing & Optimizing the Test Suite
3.1 Basic Testbench Construction
3.2 Coverage Directed Testbenches
3.3 Testbench for a Single Module
3.4 Dealing with Multiple Testbenches
3.5 Improving Your Verification Strategy
3.6 Test Equivalence & Test Dominance
3.7 Merging Testbench Results
3.8 Optimizing the Testbenches
1 Identifying Testbenches for ECO
2 Open Discussion
1st Day (1:00PM ~ 4:00PM)
1. Transaction Level Verification In Depth
1. 1 Concepts in Transaction-based Verification Environment: Transactions, Transaction Verification Models & Transaction-based Tests
1.2 Communication View of Transaction Level Modeling - Time Accuracy
1.3 Computation View of Transaction Modeling - Cycle Accuracy
1.4 Transaction Modeling Methodology & Flows
1.5 Testbench Automation for Smart Verification: Deterministic Tests, Directed Random Tests & Trace-driven Tests
1.6 The Layered Testbench Architecture
1.7 Data Introspection: Static Extension Vs Dynamic Extension
1.8 Randomization Issues: Weighted Vs Constrained
1.9 Constraints Creation & Handling: Soft Vs Hard; Flat Vs Hierarchical
1 Transaction Recording & Monitoring
2 Timing Diagram based Modeling & Automatic Testbench Generation
2.1 Template Diagram and New Transactions
2.2 Extracting MUT Ports into a Timing Diagram
2.3 Transaction Level Variables
2.4 Diagram Level Class Methods
2.5 Transaction Architecture
2.6 Diagram Properties & Settings
1 Verification Flow in Testbench Pro
2 Case Study I: C++ Modeling & Automatic Testbench Generation Using Testbench Pro
3 Open Discussion
2nd Day (9:00AM ~ 12:00AM)
1. C++ based Modeling & Automatic Testbench Generation
1.1 C++ Design Flow for HW Modeling
1.2 Bus Functional Model (BFM) Design
1.3 Modeling Memory-mapped I/O
1.4 Modeling interrupt-driven I/O
1.5 Performance Estimation with BFM
1.6 On HW/SW Synchronization
1.7 SW Simulation with Instruction Set Simulator (ISS)
1 On Integrating an BFM & an ISS
2 Classes and Variables in TestBencher Pro
2.1 Class Libraries
2.2 Classes
2.3 Variables
2.4 Variables and Class Field Properties
2.5 Data Packing
2.6 Class Methods
2.7 Constrained Random Number Generation
2.8 File I/O Variables
1 Importing Fields from a Template File
2 Open Discussion
2nd Day (1:00PM ~ 4:00PM)
1. Test Bench Techniques in TestBencher Pro
1.1 Master and Slave Transactions
1.2 Waiting for Signal Transitions
1.3 Burst Mode Transactions
1.4 Conditionally Moving Signal Edges (Sweep Tests)
1 Reading and Writing Serial Data
2 Tricks on Testbench Authoring& Design Debugging
2.1 Partition of Responsibility
2.2 Cause & Effect Testing
2.3 Complex Concurrency
2.4 Constrained Random Testing
2.5 Creating & Turning Custom Verification Environment through Off-the- Shelf-Components & Your Own In-house Components
1 Leveraging Your Verification Environment through Daily Build/Test/Release and Milestone based Synchronization & Stabilization
2 Case Study II: C++ based Transaction Level Modeling & Automatic Testbench Generation Using Testbench Pro
3 Open Discussion
© Copyright 2004-2007 Hometown Innovation Automation Inc
All Rights Reserved
Back to Home Page