Advanced IC Design and Software Engineering Training

Very/Ultra Deep Sub-Micron (VDSM) Issues in SoC Design Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1 Opening Remark

2 New Challenges Facing SoC Design in VDSM/UDSM Era
2.1 The Timing Closure Challenge
2.2 The Low Power Challenge
2.3 The Signal Integrity Challenge 1 The Design Process Challenge 2 COT (Customer Owned Tooling) Flow for SoC

3.1 Design Flows: FPGA, ASIC & COT
3.2 Libraries & IP in COT Flow: Live By the Model, Die By the Model
3.3 From Algorithm to System & From RTL to GDSII
3.4 Migrating from ASIC Flow to COT Flow
3.5 COT Flow Setup, Validation & Optimization
3.6 Product Definition, Design & Development, Post Silicon & Production of in COT Flow
3.7 The Timing Convergence, Signal Integrity & Design Process Challenge in COT Flow
3.8 Industry-strength COT Flow for SoC Design at a Glances 1 2 Cents for COT Flow for SoC Design 2 Open Discussion

1st Day(1:00PM ~ 4:00PM) 1. Layout Parasitic Extraction & Delay Calculation in Depth
1.1 Overview of DRC, LVS & LPE
1.2 Layout Parasitic: Parasitic Resistance, Parasitic Capacitance, Parasitic Inductance
1.3 On Resistive Shielding & Effective Capacitance
1.4 On Resistance Extraction
1.5 On Capacitance Extraction
1.6 The Inductance Effect
1.7 3-D TCAD Field Solver for Parasitic Capacitance Models
1.8 Template-based 3-D Extraction Engine
1.9 Parasitic Capacitance Modeling Techniques: Lookup Tables & Equations
1.10 Extraction of Power Nets, Clock Nets & Their Parasitic
1.11 Cell Timing Model Characterization: Table-based Model Vs. K-factor Model
1.12 Environment-dependent Driver Model in Delay Calculation
1.13 Path Tracing Algorithm in Delay Calculation
1.14 The Impact of Delay Calculation on Static Timing Analysis 1 A Comparison of Commercial RC Extraction & Delay Calculation Tools 2 Open Discussion

2nd Day (9:00AM ~ 12:00AM) 1. Timing Closure in Depth
1.1. The Problem of Wireload Models
1.2. RTL Floorplanning
1.3 In-Placement Optimization (IPO)
1.4 Concurrent Logic & Physical Optimization
1.4.1 Timing-frozen Logic Synthesis Vs. Timing-driven Logic Synthesis
1.4.2 The Logic Effort Concept
1.4.3 Size-driven Logical Effort based Synthesis
1.4.4 Apply Abstract Cell Concept in Predicting Path Delays
1.4.5 The Impact of Library Quality on Timing Closure
1.4.6 Stage Number and Gate Size Determination in Minimizing Path Delay
1.4.7 Size-Driven Placement and Load-Driven Routing
1.5 Post-Layout Optimization (PLO) 1 A Comparison of Commercial Timing Closure Tools 2 Open Discussion

2nd Day(1:00PM ~ 4:00PM) 1.Signal Integrity In Depth
1.1 Crosstalk, Electromigration & IR Drop
1.2 The Interrelated Design/Integrity Issues
1.3 The Concept of Timing Window
1.4 Crosstalk Delay In Depth
1.5 Crosstalk Noise In Depth
1.6 Power Analysis & Eletromigration
1.7 The Correctness-by-Construction Approach for Signal Integrity 1 A Comparison of Commercial Signal Integrity Analysis & Optimization Tools 2 IC Design Process Issues for SoC under COT

2.1 The Design Success Triangle: Process, People & Technology
2. Design Artifacts Tracability & In-house Tool Demo
2.2 Version Control In Depth & CVS Demo
2.3 Change Request Management & IssueView Demo
2.4 On Automatic Regression Test & Quality of Result (QoR) Test & In-house Tool Demo
2.5 Multi-team/Multi-site Design Activity & ClearCase, LSF Introduction
2.6 Design Process Setup, Validation, Measurement & Optimization ? Do We Need IC Design CMM?
3. Open Discussion

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