Advanced IC Design and Software Engineering Training

Advanced Physical Synthesis in COT FlowProgram Agenda (Subject to Change without Notice)

1. Overview of Physical Synthesis
1.1 Technology Scaling Trends in VDSM Era
1.2 Desi gn productivity Gap in IP-based SoC Era
1.3 Key Design Challenges: timing closure, signal integrity, high performance & low power
1.4 Optimization Space at Physical Level
1.5 Role of Static Timing Analysis at Physical Level
1.5.1 Synthesis View - Correctness through Construction
1.5.2 Analysis View - Search & Refine
1.6 Implications for Physical Synthesis in Achieving Timing Closure & Higher Performance 1 Implications for P&R in Achieving Signal Integrity 2 Fundamentals & Advanced Topics in Physical Synthesis

2.1 Floorplanning: Motivation, Key Algorithms & Implementations
2.1.1 RTL Floorplanning
2.1.2 Physical Floorplanning
2.2 Placement: Motivation, Key Algorithms & Implementations
2.3 Routing: Motivation, Key Algorithms & Implementations
2.3.1 Global Routing
2.3.2 Detailed Routing
2.3.3 Special Routing: Clock Routing, Power Routing
2.4 Physical Synthesis: ASIC Flow Vs COT Flow
2.5 Physical Synthesis Interaction with RTL Floorplanning & Logic Synthesis 1 Physical Synthesis Interaction with Extraction, Analysis & Performance Validation 2 Case Study I: A Comparison of Physical Synthesis Flows - Timing-driven Flow Vs Timing-fixed Flow 3 Open Discussion

DAY2 1. Physical Synthesis for Timing Closure & High Performance
1.1 The Impact of Library Quality on Timing Closure
1.2 Correctness-by-Construction Approach for Timing Closure
1.2.1 On The Built-in Timing Analysis Engine in Guiding P & R
1.2.2 P & R Engine for Timing Closure: Global Restructuring Optimization in Depth
1.3 Search & Repair Approach for Timing Closure
1.3.1 Adopting Stand-alone Timing Analysis Engine for Localized optimization
1.3.2 Repeater/Buffer Insertion for Long Wires
1.3.3 Transistor Sizing
1.3.4 High Fanout Net Optimization
1.3.5 Wire Sizing, Spacing & Shielding
1.3.6 On Fixing Functional (Hold Time) Timing Violations
1.3.7 On Fixing Speed (Setup Time) Timing Violations
1.3.8 On Fix Maximum Slew & Fanout Violations 1 Tips with Search & Repair Approach on Achieving Timing Closure Rapidly When Tools Cannot Help You That Much 2 Physical Synthesis for Signal Integrity

2.1 Nature & Impact of Interconnect: Parasitic Resistance, Capacitance & Inductance
2.2 Signal Integrity Causes: Glitch/Delay Uncertainty
2.3 Signal Integrity Effects: Crosstalk (Delay & Noise), Electromigration & IR Drop
2.4 Crosstalk: Analysis & Prevention Strategies
2.5 Electromigration: Analysis & Prevention Strategies
2.6 IR Drop: Analysis & Prevention Strategies
2.7 Correctness-by-Construction Approach for Signal Integrity
2.8 Search & Repair Approach for Signal Integrity
2.8.1 Increase Driver Strength to Reduce Critical Net's Glitch & Delay Uncertainty
2.8.2 Reduce Net Length to Reduce Aggressor Net's Strength 1 Insert Buffer to Reduces Victim's Noise 2 COT Flow for High Performance - From Physical Synthesis to Custom Methodology

3.1 Overview of COT Flow
3.2 Where Are the Speed Bottlenecks? - RTL, Gate-level & Physical Level
3.3 Re-architecting at Physical Level - Deep Pipelining
3.3 High Performance Logic - Dynamic Logic, High Speed Sequential, Combinational & I/O Cells,
3.4 High Performance Interconnect - Handcrafted Circuit Topologies: Buffered Long Wires, Balanced Clock Tree, Power Structures among Others 1 Case Study II: How a 1 Ghz, 2.5 Million Gates DSP ASIC Is Built in a Customized COT Flow? 2 Open Discussion

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