Advanced IC Design and Software Engineering Training

Timing-driven Logic Synthesis for IP-based SoC Design Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1 Opening Remark

2 RTL Design & Logic Synthesis at a Glance
2.1 The Gap between Algorithm & Architecture
2.2 Timing Model: Event-driven Vs. Cycle-based
2.3 RTL Design Flow: Top-down, Bottom-up & Meet-in-the-Middle
2.4 RTL Coding Style, Code Purification, Reusability Qualification & Code Coverage Analysis
2.5 Functional Simulation: Algorithm-level, RTL & Gate-Level
2.6 Formal Verification: Model Checking & Equivalence Checking 1 IC Design Process Issues at RTL 2 COT (Customer Owned Tooling) Flow for SoC

3.1 Design Flows: FPGA, ASIC & COT
3.2 Libraries & IP in COT Flow: Live By the Model, Die By the Model
3.3 From Algorithm to System & From RTL to GDSII
3.4 Migrating from ASIC Flow to COT Flow
3.5 COT Flow Setup, Validation & Optimization
3.6 Product Definition, Design & Development, Post Silicon & Production of in COT Flow
3.7 The Timing Convergence, Signal Integrity & Design Process Challenge in COT Flow
3.8 Industry-strength COT Flow for SoC Design at a Glances 1 2 Cents for COT Flow for SoC Design 2 Open Discussion

1st Day(1:00PM ~ 4:00PM)
1. Logic Synthesis Algorithm In Depth
1.1 Technology Independent Combinational Optimization: Refactoring, Redundancy Removal
1.2 Technology Mapping: Area-driven, Performance-driven & Power-driven
1.3 Technology Dependent Combinational Optimization: Gate Sizing, Pin Swapping, Buffering/Unbuffering, Remapping, Gate Cloning among others 1 Sequential Synthesis & Optimization: State Assignment, State Minimization & Retiming 2 Open Discussion

2nd Day (9:00AM ~ 12:00AM) 1. Logic Synthesis In Practice
1.1. Design Planning, Block Partitioning & Timing Budgeting
1.2. Individual Block Synthesis
1.3. Top-level Integration
1.4. Trade-off among Performance, Size & power
1.5. Static Timing Analysis
1.6. Equivalence Checking
1.7 Clock Tree Synthesis
1.8 Scan-based DFT 1 IP Integration Issues 2 Logic Synthesis Coupled with Physical Synthesis for Rapid Timing Closure

2.1 In-placement Logic Optimization (IPO) Vs. Post-Layout Optimization (PLO)
2.2 Timing-frozen Logic Synthesis Vs. Timing-driven Logic Synthesis
2.3 The Logic Effort Concept
2.4 The Impact of Library Quality on Timing Closure
2.5 What Can We Do to Achieve Rapid Timing Closure with a Traditional Logic Synthesizer?

3.Open Discussion

2nd Day (1:00PM ~ 4:00PM) 1.IC Design Process Issues for SoC under COT 1.1 The Design Success Triangle: Process, People & Technology
1.2 Design Artifacts Tracability & In-house Tool Demo
1.3 Version Control In Depth & CVS Demo
1.4 Change Request Management & IssueView Demo
1.5 On Automatic Regression Test & Quality of Result (QoR) Test & In-house Tool Demo
1.6 Multi-team/Multi-site Design Activity & ClearCase, LSF Introduction 1 Design Process Setup, Validation, Measurement & Optimization ? Do We Need IC Design CMM? 2 Open Discussion

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