Advanced IC Design and Software Engineering Training

ATPG, DFT & BIST for ASIC/SoC (June)Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1．Opening Remark

2．Testing in IC Design Flow
2.1 What & Why Manudacturing Test?
2.2 IC Manufacturing Defects, Fault Modeling & Fault Simulation
2.3 Test Specification , Test Planning in Test Process
2.4 Test Programming & Test Result Analysis
2.5 ATPG at a Glance
2.6 DFT for ASIC at a Glance
2.7 BIST for SoC at a Glance
2.8 Functional Testing Vs Diagnosis Testing 1 On Using ATE for Chip Debugging 2 ATPG In Depth

1st Day pm 1.1 Fault Simulation & Fault Grading
1.2 Testability Measurement: Controllability, Observability, Test Coverage
1.3 Combinational ATPG & Leading Algorithms
1.4 Sequential ATPG & Leading Algorithms
1.5 Memory Test, CPU/MCU Test
1.6 Delay Test, IDDQ Test
1.7 Test Pattern Compression
1.8 ATPG on a Boundary Scan Design
2. Open Discussion

1st Day(1:00PM ~ 4:00PM) 1. DFT In Depth
1.1 Components of DFT Strategy: Full Scan Vs Partial Scan
1.2 Scanable Sequential Elements (Registers & FFs) & Scan Chain Design
1.3 Design Rule Checking
1.4 Scan Chain Insertion & Reording
1.5 DFT Flow 1 DFT‘s Impact on Timing, Area & Power ? On DFT Convergence 2 Boundary Scan (JTAG, IEEE 1149.1 in Depth

2.1 JTAG In Depth 2.1.1TAP Controller
2.1.2 Boundary Scan Registers
2.1.3 Instruction Register
2.1.4 Boundary Scan Instructions
2.2 Boundary Scan Description Language (BSDL)

3. Case Study I: Scan Design & Optimization for a Custom Logic Block in SoC

4. Open Discussion

2nd Day (9:00AM ~ 12:00AM) 1. BIST in Depth
1.1 BIST Process
1.2 BIST for SoC
1.3 BIST Pattern Generation
1.4 BIST Response Compaction 1 Aliasing Probability 2 Memory BIST In Depth

2.1 Memory Fault Models
2.2 Memory BIST flow
2.3 Inserting Memory BIST structures
2.4 Memory BIST Variations
2.5 Verifying Memory BIST Logic 1 Inductive Fault Analysis 2 Logic BIST In Depth

3.1 Built-in Logic Block Observer (BILBO)
3.2 Circular Self-Test Path (CTSP) BIST
3.3 Circuit Initialization
3.4 Loop-back HW 1 Test Point Insertion 2 Open Discussion

2nd Day(1:00PM ~ 4:00PM) 1. Specific Issues in High Performance ASIC Testing In Depth
1.1 Check Design for Scan Compliance
1.2 Indentify & Correct Gated Clock Violations
1.3 Identify and correct asynchronous set or reset violations
1.4 DFT issues with tristate buses
1.5 DFT issues for bidirectional package pins
1.6 Insert scan chains at the block level
1.7 Preview fault coverage within DFTC
1.8 Make trade-offs between scan-chain count and tester time
1.9 How to minimize package-pin count
1.10 How to develop a design-specific test initialization procedure 1 How to maximize ATPG performance 2 Specific Issues in IP-based SoC Testing In Depth

2.1 Testing of Commodity-IP Core & Glue Logic
2.2 Testing of Memory Core
2.3 Testing of Start-IP Core
2.4 Testing of Analog & Mixed-signal Cores
2.5 The Integrated Testing Strategy for SoC
2.6 A Comparison of Commercial Testing Tools

3．Case Study II: BIST Design for a Custom On-Chip Memory Block in SoC

4．Open Discussion

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