Advanced IC Design and Software Engineering Training

Advanced High Performance RTL Design From Algorithm Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1 Opening Remark

2 High Speed RTL Design at Algorithm-level
2.1 High Speed Techniques Revisited
2.1.1 Algorithm Design & Optimization for High Speed
2.1.2 RTL Design for High Speed ? Our Key Focus
2.1.3 Setup Time Vs Hold Time ? Speed Constraint Vs Functional Constraint
2.1.4 Minimizing the Effect of Clock Jitter & Clock Skew: Clock Tree Synthesis/Design Vs On-chip PLL
2.1.5 Reduce the Delay of Combinational Path: Concurrent, Pipelining & Logic Restructuring
2.1.6 High Speed Library Design: Clocked Elements & Combinational Elements
2.2 Computation Models: Control-flow, Data-flow & Hybrid
2.3 Timing Models: Untimed Vs Timed (Cycle-based & Discrete Event)
2.4 Algorithm Design, Specification & Optimization in HLL: C, C++ or MatLab
2.4.1 Running Time Complexity Vs Memory Complexity
2.4.2 Fixed Point Approximation of Floating Operations
2.4.3 Techniques on Algorithm Optimization for High Speed
2.5 Behavioral/Transaction-level Design, Specification & Optimization in System-level Design Language: Cycle-based C, SystemC or SystemVerilog
2.5.1 Why Transaction-level Modeling Is Necessary?
2.5.2 Write Your C Code in Cycle-based ?
2.5.3 SystemC In Depth 1 SystemVerilog at a Glance 2 The Essence of High Speed RTL Design

3.1 Temporal Domain & Spatial Domain of HW
3.2 Scheduling, Resource Allocation and Binding
3.3 Harvard Architecture Vs Princeton Architecture
3.4 Controller & Datapath
3.5 Controller: Hardwired Vs. Programmable
3.6 FSM: Mealy Machine Vs. Moore Machine
3.7 Datapath: Regular Vs. Irregular
3.8 High Performance Datapath at a Glance
3.9 High Performance Memory Architecture at a Glance
3.10 High Performance Bus Architecture at a Glance 4．Open Discussion

1st Day 1:00PM ~ 4:00PM 1. Principles of Scalable Performance
1.1 Performance Metrics & Measures
1.2 Speedup Performance Laws
1.3 Scalability Analysis & Approaches 1 Issues on Trade-off among Performance, Area & Power 2 High Speed RTL Design Using ASM

2.1 On the ASM Chart
2.1.1 ASM Notations
2.1.2 The Theory behind ASM
2.2 Scheduling, Resource Allocation & Binding
2.3 Advanced ASM Techniques
2.4 The Trade-off between Mealy Machine & Moore Machine
2.5 The Trade-off between Datapath & Controller 1 RTL design in the SoC Context - When You Have to Deal with 3rd-Party IP) 2 Hard-wired Controller based High Performance RTL Design

3. The Cycle-based Delay Model at RTL
3. Bus Functional Model
3. Multi-cycle& Chaining
3. Latency Vs. Throughput
3. Pipelining, Currency & Superscalar
3. Hard-wired Controller In Depth: Next State Logic, State Register & Output Logic
3. Control Scheme: Centralized Control Vs Distributed Control
3. Hard-wired Controller (FSM) Partitioning In Depth 1 The Trade-off between Hard-wired Controller & Datapth 2 Case Study I: Design a Superscalar FFT (Fast Fourier Transform) IP Block with ASM5. Open Discussion

2nd Day (9:00AM ~ 12:00AM) 1. High Speed Techniques at RTL In Depth
1.1 Static (Linear) Pipelining Vs Dynamic (Nonlinear) Pipelining
1.2 Controller Pipeline Design Vs Instruction Pipeline Design
1.3 Datapath Pipeline Design Vs Arithmetic Pipeline Design
1.4 Supersclar Design Vs Superpipeline Design
1.5 Asynchronous Pipelining (Micropipeline) at a Glance 1 Other Performance Improvement Techniques at a Glance: Cache Memory, Branch Prediction, Out-of-Order Execution and Register Renaming, Speculative Execution 2 Microprogrammed Control based High Performance RTL Design

2.1 MCU, CPU & DSP
2.2 CISC, RISC, SuperScalar & VLIW
2.3 The Impact of ISA on Programmable on Microprogrammed Control based RTL Design
2.3.1 Data Types
2.3.2 Instructions Formats & Types
2.3.3 Addressing Modes2.3.4 Flow of Control
2.4 The Demands of Programmable Microarchitecture on Compiler
2.4.1 The Frontend of a Compiler: Processor & Optimizer
2.4.2 The Backend of a Compiler: Assembler, Linker & Loader
2.5 The Design of Custom ISA (Microinstructions) for Microprogrammed Control
2.6 The Design of Sequencer for Microprogrammed Control
2.6.1 Design Considerations
2.6.2 Sequencing Techniques
2.6.3 Address Generation
2.7 Issues on Designing Pipelined Sequencer3. Open Discussion

2nd Day (1:00PM ~ 4:00PM) 1．Advanced Verilog for High Performance RTL Design 1.1 Simulation View Vs Synthesis View ? How to Deal with Mismatches?
1.2 Clocked Building Blocks: Edge-based Design Vs Latch-based Design
1.3 Interconnection Structures: Bus-based Vs MUX-based
1.4 FSM State Encoding &State Minimization for Performance
1.5 On Addressing Wide Decoder Issues
1.6 Design Partitioning for Performance
1.6.1 Partitioning Rules
1.6.2 Synthesis Partitioning
1.6.3 FSM partitioning
1.7 Synchronous Logic Rules for High Performance
1.8 Clocking Strategies for High Performance
1.9.1 Edge-based Vs Latch based
1.9.2 On Clock Domain Interfacing: Synchronization Mechanism In Depth
1.10 Issues on Memory Interleaving Modeling 1 Issues on Pipelining Modeling 2 Case Study II: Design CISC (PDP-8 subset) & RISC (ARM subset) CPU with ASM 3 Open Discussion

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