Synthesis for Timing Closure & Signal Integrity Program Agenda (Subject to Change without Notice) Date Agenda
1st Day
(9:00AM ~ 12:00AM)
1 Opening Remark
2 A Quick Overview of Advanced Logic Synthesis for IP based SoC Integration
2.1 The SoC Design Challenges: IP Reuse, Timing Closure, Signal Integrity, Performance Bottleneck & Low Power Requirement
2.2 The Problems with Traditional Synthesis: The Decoupling of Logic & Layout
2.3 Solution on Minor Improvements of Traditional Synthesis: Layout-driven Synthesis Vs Synthesis-driven Layout
2.4 Solution on EDA Flow Change: COT Flow for IP-based SoC Design
1 The Novel Concept of Logic Effort for Advanced Logic Synthesis ? The Breakthrough Solution
2 The Essence of Logical Effort
3.1 Definition of Logical Effort & Electrical Effort
3.2 Calculating Logical Effort
3.3 Choose the Best Numbers of Stages
3.4 Minimize Delay along a Path
3.5 Branches & Interconnect
3.6 On Wide Structures: Decoders & Multiplexes
3.7 A Design Procedure for Logical Effort Based Design
1 Insights from Logical Effort
2 Open Discussion
1st Day(1:00PM ~ 4:00PM)
1. Logical Effort based Advanced Logic Synthesis Techniques
1.1 Unmapping/Mapping
1.2 Gate Sizing
1.3 Gate Cloning
1.4 Redundancy Removal
1.5 Pin Swapping
1.6 Constant Propagation
1.7 Logic Restructuring
1.8 Buffer Insertion & Deletion
1 Retiming
2 Case Study I: Ethernet MAC 10/100 Mbps Block Design3. Open Discussion
2nd Day
(9:00AM ~ 12:00AM)
1. Logical Effort based Advanced Logic Synthesis for Timing Closure
1.1 Timing Closure Challenges in SoC Design
1.2 Size-driven Logical Effort based Synthesis Vs. Timing-driven Synthesis
1.3 Apply Abstract Cell Concept in Predicting Path Delays
1.4 The Impact of Library Quality on Timing Closure
1.5 Stage Number and Gate Size Determination in Minimizing Path Delay
1.6 Size-Driven Placement and Load-Driven Routing
1.7 The Correctness-by-Construction Approach for Signal Integrity
1.8 A Comparison of Commercial Timing Closure & Optimization Tools
1 Logic Effort based Advanced Logic Synthesis for Timing Closure ? Search & Repair In Practice
2 Open Discussion
2nd Day(1:00PM ~ 4:00PM)
1. Logical Effort based Advanced Synthesis for Signal Integrity
1.1 Nature & Impact of Interconnect: Parasitic Resistance, Capacitance & Inductance
1.2 Crosstalk (Delay & Noise), Electromigration & IR Drop
1.3 Delay Models In Depth: Elmore Delay, AWE among Others
1.4 The Concept of Timing Window
1.5 On Dealing with Crosstalk: Crosstalk Delay & Crosstalk Noise In Depth
1.6 On Dealing with Eletromigration
1.7 On Dealing with IR Drop
1.8 Impacts of Packaging & Bonding
1.9 The Correctness-by-Construction Approach for Signal Integrity
1.10 A Comparison of Commercial Signal Integrity Analysis & Optimization Tools
1 Logic Effort based Advanced Logic Synthesis for Signal Integrity ? Search & Repair In Practice
2 Case Study II: PCI Bus Controller Design
3 Open Discussion
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