Advanced IC Design and Software Engineering Training

Advanced RTL Design - From Algorithm to System Program Agenda (Subject to Change without Notice) Date Agenda

1 Opening Remark

2 RTL Design under From Algorithm to System Context
2.1 Design Flows: FPGA, ASIC & COT
2.2 Design Views in Y Chart: Algorithmic, Structural & Physical
2.3 Migrating from ASIC Flow to COT Flow: What Is It & How It Can Be Done?
2.3 Computation Models: Control-flow, Data-flow & Hybrid
2.4 Timing Models: Untimed Vs Timed (Cycle-based & Discrete Event)
2.5 Algorithm Design, Specification & Optimization in HLL: C, C++, Java & MatLab
2.6 Behavioral/ Transaction-level Design, Specification & Optimization in System-level Design Language: SystemC & SystemVerilog In Depth
2.7 HW/SW Co-design: Partitioning, Co-verification & Co-validation
2.8 EDA Flow Setup, Validation & Turning with Scripting Languages: Tcl & Perl In Depth
2.9 Verification & Validation for RTL Design ? Solutions to Verification Challenges
2.9.1 Functional Simulation & Timing Simulation
2.9.2 Formal Verification: Equivalence Checking & Property Checking
2.9.3 Static Timing Analysis & Optimization
2.9.4 FPGA based Rapid Prototyping
2.10 Bridging Logic Design to Physical Design ? Solutions to Timing Closure Challenges
2.10.1 Physical-driven Logic Synthesis Vs Logic-driven Physical Synthesis

2.10.2 Timing-driven Synthesis Vs Timing-frozen Synthesis
2.11 On RTL Design Frontier
2.11.1 High Speed, Low Power Design: Do What EDA Tools Cannot Do
2.11.1.1 Setup Time Vs Hold Time ? Speed Constraint Vs Functional Constraint
2.11.1.2 Minimizing the Effect of Clock Jitter & Clock Skew: Clock Tree Synthesis/Design Vs On-chip PLL
2.11.1.3 Reduce the Delay of Combinational Path: Pipelining Vs Logic Restructuring
2.11.1.4 High Speed Library Design: Clocked Elements & Combinational Elements
2.12 IP-based SoC Design Reuse: Never Reinvent Your Wheel
2.12.1 Commodity IP Vs Star-IP ? An Overview on ARM & MIPS
2.12.2 What Make IP Integration Difficult? 1 Our Unique View on IP-based SoC Integration 2 Open Discussion

1st Day 1:00PM ~ 4:00PM 1. The Essence of RTL Design
1.1 Temporal Domain & Spatial Domain of HW
1.2 Scheduling, Resource Allocation and Binding
1.3 Controller & Datapath
1.4 Controller: Hardwired Vs. Programmable
1.5 FSM: Mealy Machine Vs. Moore Machine
1.6 Datapath: Regular Vs. Irregular
1.7 Build High Performance Datapath
1.8 Memory Architecture In Depth: On-chip Flash, ROM, DRAM, SDRAM & CAM 1 Bus Architecture In Depth: High Performance Vs Low Cost 2 RTL Design Using ASM

2.1 On the ASM Chart
2.2 ASM Notations
2.3 The Theory behind ASM
2.4 Scheduling, Resource Allocation & Binding
2.5 Advanced ASM Techniques
2.6 The Trade-off between Mealy Machine & Moore Machine
2.7 The Trade-off between Datapath & Controller 1 RTL design in the SoC Context - When You Have to Deal with 3rd-Party IP) 2 Case Study I: Designing an SRA (Square Root Approximation) Block

3. Open Discussion

2nd Day(9:00AM ~ 12:00AM) 1. Hard-wired Controller based RTL Design with ASM for Speed & Cost
1.1 The Cycle-based Delay Model
1.2 Multi-cycle, Chaining and Pipelining
1.3 Latency Vs. Throughput
1.4 Pipelining, Currency & Superscalar 1 Architecture-level Trade-off between Speed & Cost 2 Advanced Verilog for RTL Design

2.1 Data Representation: Issues on Floating to Fixed-Point Optimization
2.2 Combinatorial Building Blocks: MUX, Decoders, Encoders & Priority encoders
2.3 Clocked Building Blocks: Edge-based Design Vs Latch-based Design
2.4 Interconnection Structures: Bus-based Vs MUX-based
2.5 Arithmetic Building Blocks: Custom Vs Synthesis-based
2.5.1 Adders & Subtractors
2.5.2 Multipliers & Divisors
2.6 Datapath Functions: Organization and types of comparators, counters and ALUs
2.7 Finite State Machines: State Encoding &State Minimization
2.8 Memory structures: Basics, synchronous and dual port RAM, LIFO and FIFO structures
2.9 Partitioning Issues
2.91.1 Goals and Rules
2.91.2 Synthesis Partitioning 1 FSM partitioning 2 Case Study II: Design a Pipelining FFT (Fast Fourier Transform) Chip 3 Open Discussion

2nd Day(1:00PM ~ 4:00PM) 1. Programmable Controller based RTL Design with ASM for Speed & Cost
1.1 MCU, CPU & DSP
1.2 CISC, RISC, SuperScalar & VLIW
1.3 The Impact of ISA on Programmable Microarchitecture
1.4 The Demands of Programmable Microarchitecture on Compiler
1.5 Controller Design for Programmable Microarchitecture
1.5.1 The Design of Custom ISA
1.5.2 The Design of Sequencer
1.5.3 On Decoding Logic
1.5.4 The Design of Custom Datapath
1.5.5 Memory Architecture Issues
1.5.6 Bus Architecture Issues 2ㄝAdvanced Verilog for RTL Design 每 Part II 2 Simulation View Vs Synthesis View ? How to Deal with Mismatches?
2.2 Synthesizable Subset of Verilog
2.3 RTL Coding Styles for Verilog: Synthesizability & Reusability
2.4 Design for Performance/Cost Trade-off: Partitioning & Timing
Budgeting Verilog Hierarchy Revisited
2.5 Specific Design Issues
2.5.1 On Dealing with Long Wires
2.5.2 Gated Clock Vs Clock Enable
2.5.3 On Glitch Elimination Vs Redundancy Removal
2.5.4 Asynchronous Design and Metastability
2.5.4.1 Asynchronous Design Basics
2.5.4.2 Metastability and Mean Time Between Failure (MTBF) Calculation
2.5.4.3 On Handling Asynchronicity
2.5.4.4 On Multi-clock domain interfacing
2.5.5 On Design-For-Testability (DFT)
2.5.6 On Clock-Tree-Synthesis (CTS)
2.6 Trade-off between Operating Speed and Latency
2.7 Scalable and Parameterized Design ? The 1st Step for IP-based SoC Design

3. Case Study I: Design CISC (PDP-8 subset) & RISC (ARM subset) CPU Using ASM4. Open Discussion

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