Static Timing Analysis & Optimization Techniques Program Agenda (Subject to Change without Notice) Date Agenda
1st Day
(9:00AM ~ 12:00AM)
1 Opening Remark
2 Advanced Static Timing Analysis in Modern IC Design Context
2.1 Challenges in Design Crisis: Moore¡®s Law, Exponentially Growing Bug Rate, Picky Customer, Aggressive Competition & Time-to-Market
2.2 The Four Leading Design Constraints: Die Size, Performance, Power & Reliability
2.3 The Four Basic Questions in Design Refinement
2.3.1 How to Capture a Design: Language, Abstraction Level & Model Completeness? ? Functional Aspect Vs Constraint Aspect
2.3.2 How to Verify the Captured Design Is correct? ? Dynamic Validation Vs Formal/Static Verification
2.3.3 How to Transform a Design? ? Synthesis, Manual & Hybrid
2.3.4 How to Verify the Transformed Design Is correct? - Dynamic Validation Vs Formal/Static Verification
2.4 Static Timing Analysis in Verifying Design Capture & Design Transformation
1 Static Timing Analysis for Timing Closure & Performance Turning
2 Fundamental Concepts in Advanced Static Timing Analysis
3.1 Synchronous Design Vs Asynchronous Design
3.2 Synchronous Design : Edge-trigged Design Vs Level-sensitive Design
3.3 Setup Time (Speed) Constraint Vs Hold Time (Functional) Constraint
3.4 Timing Paths: Single Path, Multi-Path & False Path
3.5 Source & Network Latency: Clock Skew Vs Clock Jitter
3.6 The Clocking Scheme & The Clock Network Topology
3.7 The Impact of Parasitic on Static Timing Ansalsis: Gate Delay Vs Wire Delay
3.9 Timing Model In Depth
3.9.1 User View: Netlist, Library, Constraints & Wire Models
3.9.2 Static Timing Analyzer View: Evenets, Relations
4. Open Discussion
1st Day(1:00PM ~ 4:00PM)
1. Advanced Static Timing Analysis ? The Specification View
1.1 Basic Timing Constraints: Operating Condition, Drive Resistance,
Maximum Loading Capacitance, Maximum Transition Time, Maximum Fanout, Input Delay, Output Delay, Clock Skew, Clock Cycle among Others
1.2 Advanced Timing Constraints: False Path, Multicycle Path, Maximum Path Delay, Minimum Path Delay, Path Grouping
1.3 Clocking Constraints Issues
1.3.1 Pre-Layout Vs Post-Layout
1.3.2 Primary Clock Vs Derived Clock
1.4 Timing Constraints Vs Area Constraints
1.5 Manual Timing Specification Vs Automation Timing Budgeting
1 Architectural Design Space Exploration Vs Timing Constraints Design Space Exploration ? Always Doubt Whether It Is Your Architectural Issues Not When Reasonable Timing Constraints Cannot Be Met?
2 Case Study I: Static Timing Analysis & Optimization of USB 2.0 Controller
3 Open Discussion
2nd Day
(9:00AM ~ 12:00AM)
1. Advanced Static Timing Analysis ? The Verification View
1.1 Static Timing Analysis Algorithms In Depth
1.1.1 Depth First Search (DFS) Vs Breadth First Search (BFS)
1.1.2 Arrival Time & Require Time Calculation: Node vs Path
1.1.3 Timing Path Tracing
1.1.4 Slew Calculation
1 Timing Path Reporting & Analysis ? Where Are the Timing Bottlenecks?
2 Case Analysis, Mode & Path Exceptions
3 Incremental Static Timing Analysis in Design Syntheiss: The Correctness-through-Construction Approach
4 Design Rule Fixing: Delay Prioritized Vs DRC Prioritized
5 The Impact of Synthesis/Compilation Strategies
6 On Design Backannotation in Static Timing Analysis
7 Static Timing Analysis Checklist & Tips2. Open Discussion
2nd Day(1:00PM ~ 4:00PM)
1. Advanced Static Timing Analysis ? The Optimization View
1 Gate-level View of Performance Constraints: Combinational Path Delay, DFF¡®s Setup Delay, DFF¡®s Clock to Output Delay & Clock Skew
2 Timing Path Reporting & Analysis ? How to Fix the Timing Bottlenecks?
3 Incremental Static Timing Analysis in Design Optimization: The Search-and-Repair Approach
4 The Importance of Tcl/Perl Scripting & How to Apply It for Static Timing Optimization through NetlistManipulation
5 Feasible Timing Optimization Techniques: Logic Restructuring, Hierarchy Removing, Clock NetworkOptimization & Migrating to High Performance Libraries
6 The Impact of CTS & DFT on Design Performance & How to Minimize Their Impacts
7 Static Timing Optimization Checklist & Tips. Case Study II: Static Timing Analysis & Optimization of CRT/LCD Controller
3. Open Discussion
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