Advanced Symposium on IP based SoC Integration Program Agenda (Subject to Change without Notice) Date Agenda
1st Day
(9:00AM ~ 12:00AM)
1 Opening Remark
2 Industry-strength SoC Design Methodology: The State-of-the-art
2.1 System-level Synthesis: HW/SW Co-design, Co-simulation & Co-verification
2.2 Design for Timing Closure: Logic Design Issues & Physical Design Issues
2.3 Design for Verification: Verification Strategy
2.4 Design for Low Power
2.5 Design for Signal Integrity
2.6 Design for High-Speed: a Possibility or a Hyper?
1 SW Aspects of SoC: ISA, RTOS, Customizable Compiler & Debugger
2 IP-based SoC Design Issues
3.1 Design Flows: FPGA, ASIC & COT
3.2 From Algorithm to System & From RTL to GDSII
3.3 Migrating from ASIC Flow to COT Flow
3.4 System Architecture & On-chip Buses
3.5 RTL Coding Guide Lines for Design Reuse
3.6 Design & Development, Post Silicon & Production of in COT Flow
1 Design Process Challenge in COT Flow: Version Control, Bug Tracking, Regression Testing & QoR Testing, Distributed Development & Management among Others
2 Open Discussion
1st Day(1:00PM ~ 4:00PM)
Lab 1: Design a Pipelined Fixed Point Multiplier with Read & Write FIFO by Instantiating CorrespondingIP
2nd Day(9:00AM ~ 12:00AM)
1. IP based SoC Modeling & Specification
1.1 Hardware IP & Software IP
1.1.1 Hardware IP: Star IP (High Value IP), Standards-based IP, Commodity IP
1.1.2 Soft IP, Hard IP & Firm IP ? Pros & Cons
1.1.3 Domain-specific IP Vs Domain Independent IP
1.2 The Role of Full Custom Design in Reuse
1.3 The IP Evaluation & License Process
1.4 Design Reuse under Reusable Methodology Manual
1.5 Top-level Specification£ºC, C++, SystemC, SystemVerilog ¨C Who Is the Champion?
1.6 Constrained HW/SW Partitioning under Performance, Size & Power
1.7 Bus Architecture & Memory Architecture in IP-based SoC
1 FPGA Prototyping for IP-based SoC Golden RTL Sign-off
2 Introduction to Leading IP, IP based SoC Standards & IP based SoC EDA Tools
2.1 Star IP In-Depth: ARM Vs MIPS
2.2 Commodity IP: DesignWare anong Others
2.3 IP based SoC Standards: VSIA, OCP-IP, AMBA among Others
1 IP based SoC EDA Tools Comparison: Those from Synopsys, Mentor & Cadence- No Tools Can Make IP-based Integration Fully Automatic So Far
2 Implementing a IP-based SoC Design Process
3.1 Key Steps in Implemnenting Such a Process
3.2 Managing the Transition to Such a Process
3.3 Technical Issues in IP-based SoC Design Process
1 Non-technical Issues in IP-based SoC Design Process: Business-wise & Organizational3.5 Dealing with Legacy IP in SoC Design
2 Case Study: Design an IP-based Digital Camera SoC
3 Open Discussion
2nd Day
(1:00PM ~ 4:00PM)Lab 2: Design a Pipelined Fixed Point Division Machine with Read & Write Synchronous Dual PortMemory by Instantiating Corresponding IP
3nd Day(9:00AM ~ 12:00AM)
1. IP based SoC Synthesis & Verification
1.1. IP Selection for Your SoC ? Design Tips & Tricks
1.2. Why Soft IP Is More Favorable than Hard IP Generally?
1.3. Design Glue Logic to Hooking All Hardware IP Up ? Problems & Solutions
1.4. HW/SW Interfacing Issues: Interrupt, Memory-Mapped I/O among Others
1.5. HW/SW Co-simulation Issues
1.6. Debug Architecture & SoC Verification Environment
1 On Reusable Verification
2 Hard IP Specific Issues in IP-based SoC Design
2.1 Why & When to Use Hard IP?
2.2 Design Issues for Hard IP
2.3 Integration Issues with Hard IP
1 The Importance of Physical Design ( in COT Flow ) in Hard-IP based SoC Design
2 SW Specific Issues in IP-based SoC Design
3.1. Differentiate Your Design with SW ? Why SoC Is Superior over ASIC?
3.2 SW/HW Partitioning Issues in IP-based SoC Design
3.3 ISA Issues in IP-based SoC Design
3.4 Customer Compiler Issues in IP-based SoC Design
3.5 RTOS Issues in IP-based SoC Design
1 SW/HW Interface Issues in IP-based SoC Design
2 Open Discussion
3nd Day (1:00PM ~ 4:00PM)
Lab 3: Customizing Compiler, Debugger & RTOS for ARM-thumb ISA for IP-based SoC Design on Linux