Advanced IC Design and Software Engineering Training

Advanced Verification/Validation Techniques Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1 Opening Remark 2 Key Verification Issues for ASIC/SoC Design

2.1 ASIC/SoC Verification Goals: Efficiency & Reusability
2.2 The Verification Challenges in ASIC/SoC Design
2.3 The Big Gaps: between Algorithm & Architecture, between Design & Verification
2.4 Timing Model: Event-driven Vs. Cycle-based
2.5 Verification in ASIC Flow & COT Flow
2.6 Design Inspection & Review: Coding Style & Reusability Qualification
2.7 Formal Verification for Specification Driven Verification: Model Checking/Assertion based Property Checking & Equivalence Checking
2.8 Functional Verification for Bug Driven Verification: Simulation, Emulation & Testing
2.9 Coverage Driven Verification: Coverage Analysis 1 The Role of Languages in Verification: High-level Programming Languages, HDLs, Verification Oriented Languages & Scripting Languages 2 Design Inspection & Review In Depth

3.1 The Synthesizable Subset of RTL Verilog: What You Can Simulate Is What You Can Synthesize
3.2 The Code Review & Inspection Process
3.4 The RTL Coding Styles for Design Reuse
3.4.1 Basic Coding Practices
3.4.2 Coding for Portability
3.4.3 Guidelines for Clocks & Resets
3.4.4 Coding for Synthesis
3.4.5 Designing with Memories 1 Code Profiling 2 Open Discussion

1st Day(1:00PM ~ 4:00PM) 1. Functional Verification In Depth
1.1 Functional Verification Approaches: Testing vs. Verification
1.2 Functional Verification Tools: Syntax-sensitive Editors, Linting Tools. Simulators & Code Coverage
1.3 The Functional Verification Plan
1.3.1 The Role of the Verification Plan
1.3.2 Abstraction Level of Verification
1.3.3 Verification Strategies
1.3.4 From Specification to Features
1.3.5 From Features to Test cases
1.3.6 From Test cases to Testbenches
1.4 HDL Revisited
1.4.1 The Essence of RTL
1.4.2 Inside HDL Simulation Engine
1.4.3 HDL Portability Issues
1.5 Stimulus and Response
1.5.1 Self-Checking Testbenches
1.5.2 Complex Stimulus & Complex Response
1.5.3 Predicting the Output
1.6 Architecting Testbenches
1.6.1 Reusable Verification Components
1.6.2 Autonomous Generation and Monitoring. Input and Output Paths
1.6.3 Verifying Configurable Designs
1.7 Regression Test Revisited
1.7.1 The Golden Result Concept
1.7.2 The Version Control Systems & the Issue/Bug Tracking System
1.7.3 The Daily Build/Test/Release and Milestone-based Synchronize & Stabilize Practice
1.8 On Automatic Test Bench Generation with Guaranteed Coverage
1.9 On Layered Testbench Architecture 1 On Reusability of Testbench Components 2 Case Study I: Functional Verification of a Million Gate ASIC Design 3 Open Discussion

2nd Day(9:00AM ~ 12:00AM) 1. Equivalence Checking In Depth
1.1. Verification without Testbech ? Is That a Magic?
1.2. Binary Decision Diagram (BDD) In Depth
1.3. Combinational Equivalence Checking: Functional Checking Vs Structural Checking
1.4. Sequential Equivalence Checking: Symbolic Checking Vs Isomorphic Checking
1.5. Equivalence Checking Variations: RTL Vs. Gate Vs. Transistor-level 1 An Introduction to Commercial Equivalence Checkers 2 Property Checking In Depth

2.1 Correct Design Vs Design Correctness: Behavior Vs Property
2.2 Computation Tree Logic (CTL) In Depth
2.3 Model Checking In Depth? Does That Really Work?
2.3.1 Modeling Aspect of Model Checking
2.3.2 Specification Aspect of Model Checking
2.3.3 Verification Aspect of Mode Checking
2.4 Dynamic Property Checking (Assertion Based Property Checking)
2.4.1Structural Testing
2.4.2 Self-Checking Test Benches
2.4.3 Pattern Matching 1 Dynamic Property Checking Flow & One Example 2 HDL Code Coverage Analysis based Verification In Depth

3.1 The Principle of Code Coverage Analysis
3.2 Types of Code Coverage: Statement Coverage, Branch Coverage, Condition & Expression Coverage, Path Coverage, Toggle Coverage, Triggering Coverage & Signal Tracing Coverage
3.3 FSM Coverage In Depth
3.3.1 The FSM State Space Explosion Problem
3.3.3 Reachability Based Path Coverage
3.3.3 Manual Path Specification
3.4 Coverage Directed Verification Methodology In Depth
3.4.1Coverage Analysis in Design Flow: Algorithmic/behavioral Level, RTL & e-level
3.4.2 Practical Guidelines for Coverage Analysis 1 Coverage Measure & Targets 2 Open Discussion

2nd Day(1:00PM ~ 4:00PM) 1. Verification Architecture for Full-Chip Pre-Silicon Validation
1.1 Pre-Silicon Validation
1.1.1 Exploiting HW Concurrency
1.1.2 Automated Testbench Generation Revisited
1.1.3 Lea verging Design Know-How & Application Know-How
1.1.4 Choosing Right Abstraction Level
1.1.5 On Configurability & Reuse of Verification Environment
1.1.6 Tips on Debugging
1.1.7 The Role of Scripting Languages like Perl & Tcl in Building Your Own Verification Flow
1.2 An Architecture for Pre-Silicon Validation
1.2.1 Verification Components
1.2.2 Smart Bus Functional Models
1.2.3 Smart Bus Protocol Monitors 1 Smart Test Controller & Data Checker 2 Total Solution for Verification of ASIC/SoC - Let Us Tell You In Detail Later

2.1 Creating & Turning Your Own Efficient Verification Environment through Off-the-Shelf-Components & Your Own Custom Components 1 Leveraging Your Verification Environment through Daily Build/Test/Release and Milestone based Synchronization & Stabilization 2 Case Study II: HW & SW Combined Solution in Verifying of a Million Gate SoC Design 3 Open Discussion

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