Advanced IC Design and Software Engineering Training

From C/C++ to Synthesizable Verilog/SystemVerilog 5.3 Clocked Building Blocks: Edge-based Design Vs Latch-based Design

1 Opening Remark 2 RTL Design under From Algorithm to System Context

2.1 Design Flows: FPGA, ASIC & COT
2.2 Design Views in Y Chart:Algorithmic, Structural & Physical
2.3 Migrating from ASIC Flow to COT Flow: What Is It & How It Can Be Done?
2.4 Computation Models: Control-flow, Data-flow & Hybrid
2.5 Timing Models: Untimed Vs Timed (Cycle-based & Discrete Event)
2.6 From Business Requirement to Functional Requirement to Architectural Requirement
2.7 Functional Design Specification & Optimization in C/C++
2.8.1 System Architectural Design Specification & Optimization in SystemVerilog
2.8.2 Solution to SoC Design Challenges - Ascending from Verilog to SystemVerilog
2.8.3 Raising Abstraction Level - From RTL to Transaction-level

3. The Essence of RTL Design
3.1 Temporal Domain & Spatial Domain of HW
3.2 Scheduling, Resource Allocation and Binding
3.3 Controller & Datapath
3.4 Controller: Hardwired Vs. Programmable
3.5 FSM: Mealy Machine Vs. Moore Machine
3.6 Datapath: Regular Vs. Irregular & How to Build High Performance Datapath
3.7 Memory Architecture In Depth: On-chip Flash, ROM, DRAM, SDRAM & CAM
3.8 Bus Architecture In Depth: High Performance Vs Low Cost
3.9 RTL Design Using ASM

4. C/C++ for HW Modeling & Verification
4.1 Why C++?
4.1.1 What C Lacks?
4.1.2 What Is C++? - Data Abstraction, OO Programming & Generic Programming
4.1.3 What C++ Differs from C?
4.2 Data Abstraction, Information Hiding & Polymorphism
4.2.1 Classes Vs Objects: Static Modeling Vs Dynamic Modeling
4.2.2 Operator Overloading
4.2.3 Inheritance
4.2.3.1 Public Inheritance, Private Inheritance & Multiple Inheritance
4.2.3.2 Virtual Function In Depth: Dynamic Binding Instead of Static Binding
4.2.4 Parameterized Design: Class Templates Vs Function Templates
4.2.5 Exception Handling
4.2.6 Class Hierarchies
4.3 The Standard Library Vs Custom Library
4.3.1 Static Library Vs Dynamic (Shared) Library
4.3.2 Standard Library Organization and Containers
4.3.2 Standard Containers
4.3.3 Strings & Streams in Standard Library
4.3.4 How to Construct Your Own Library to Leverage C++'s Extensibility
4.4 Memory Management in C++
4.4.1 Memory Allocation & Deletion
4.4.2 Constructors & Destructors: Default Vs Custom
4.4.3 Copy Constructors
4.4.3 Assign Operators

5. Synthesizable Verilog at RTL - Part I
5.1 Data Representation: Issues on Floating to Fixed-Point Optimization
5.2 Combinatorial Building Blocks: MUX, Decoders, Encoders & Priority encoders
5.4 Interconnection Structures: Bus-based Vs MUX-based
5. 5 Arithmetic Building Blocks: Custom Vs Synthesis-based
5.6 Datapath Functions: Organization and types of comparators, counters and ALUs
5.7 Finite State Machines: State Encoding &State Minimization
5.8 Memory structures: Basics, synchronous and dual port RAM, LIFO and FIFO structures 1 Partitioning Issues 2 Open Discussion

Day 2 1. Hard-wired Controller based RTL Design with ASM for Speed & Cost
1.1 The Cycle-based Delay Model
1.2 Multi-cycle, Chaining and Pipelining
1.3 Latency Vs. Throughput
1.4 Pipelining, Currency & Superscalar
1.5 Architecture-level Trade-off between Speed & Cost 1 Mini Case Study: Design a Pipelined FFT Block 2 Synthesizable Verilog at RTL - Part II

2.1 Simulation View Vs Synthesis View
2.2 Synthesizable Subset of Verilog
2.3 Verilog Synthesis Styles
2.4 RTL Coding Styles for Verilog
2.5 Design for Performance/Cost Trade-off
2.5 Design for Design Reuse
2.6 Specific Synthesis-driven Modeling Issues
2.6.1 On Dealing with Large Fanins
2.6.2 On Dealing with Large Fanouts
2.6.3 On Dealing with Long Wires
2.6.4 On Glitch Elimination
2.6.5 On Dealing with Metastability
2.6.6 Gated Clock Vs Clock Enable 1 How to Avoid Synchronization Failure? 2 Programmable Controller based RTL Design with ASM for Speed & Cost

3.1 MCU, CPU & DSP
3.2 CISC, RISC, SuperScalar & VLIW
3.3 The Impact of ISA on Programmable Microarchitecture
3.4 The Demands of Programmable Microarchitecture on Compiler
3.5 Controller Design for Programmable Microarchitecture
3.5.1 The Design of Custom ISA
3.5.2 The Design of Sequencer
3.5.3 On Decoding Logic
3.5.4 The Design of Custom Datapath
3.5.5 Memory Architecture Issues 1 Bus Architecture Issues 2 Transaction Level Verification In Depth

4.1 Functional Simulation Vs Functional Code Coverage
4.2 Testbench Automation for S mart Verification: Deterministic Tests, Directed Random Tests & Trace-driven Tests
4.3. Concepts in Transaction-based Verification Environment: Transactions, Transaction Verification Models & Transaction-based Tests
4.4. The Layered Testbench Architecture
4.5 Data Introspection: Static Extension Vs Dynamic Extension
4.6 Randomization Issues: Weighted Vs Constrained
4.7 Constraints Creation & Handling: Soft Vs Hard; Flat Vs Hierarchical
4.8 Transaction Recording & Monitoring 1 Assertion Based Verification 2 Synthesizable SystemVerilog in Depth

5.1 A Better Verilog for RTL Specification
5.2 Raising Abstraction Level to Transaction Level
5.2.1 Support Complex Data Structures
5.1.2 Support Separation of Communication & Computation
5.3 Unification of Synthesis & Verification
5.3.1 Layers of Assertion: Assertion Directives, Property Declarations, Sequential Regular Expressions & Boolean Expressions
5.3.2 Interaction between Assertion & Testbench
5.3.3 Built-in Testbench Modeling: Constrained Test Generation & Functional Coverage Analysis 1 The Addition of Object Oriented Paradigm 2 Case Study: Design CISC (PDP-8 subset) & RISC (ARM subset) CPU Using ASM

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