Advanced IC Design and Software Engineering Training

ASIC/SoC Modeling, Synthesis & Verification from C Program Agenda (Subject to Change without Notice) Date Agenda

1 Opening Remark

2 Key Issues on ASIC/SoC Design & Verification
2.1 ASIC/SoC Verification Goals: Efficiency & Reusability
2.2 The Verification Challenges in ASIC/SoC Design
2.3 ASIC/SoC Design Goals: Cost (Die Size, Packaging etc.), Performance & Power
2.4 The Design Challenges in ASIC/SoC Design
2.5 The Big Gaps among Algorithm-level, Transaction-level & RTL
2.6 Computation Model (Cycle View) Vs Communication Model (Timing View)
2.7 On the Computation Bottleneck & How to Minimize Its Effect
2.8 Simulation View Vs Synthesis View 1 From HW Design to HW, SW Design to HW/SW Co-design 2 C for HW Modeling & Verification ? Part I

3.1 Why C & Why Not C++?
3.2 Advanced C Revisited
3.2.1 The Standard C Library Vs Custom C Library
3.2.2 Memory Management in C
3.2.3 Will C Work on Object-Oriented Modeling?
3.3 SW Engineering Aspect of C for HW Design & Verification
3.3.1 Algorithm Complexity: Running Time Vs Memory Efficiency
3.3.2 Algorithm & Data Structures
3.3.2 Requirement Elicitation & Management
3.3.3 Unit Test, Integration Test, System Test, Regression Test & QoR Test
3.3.5 Performance Turning, Code Coverage & Memory Leakage Detection
3.3.6 Extreme Programming at Practice
3.3.6.1 Version Control & Bug Tracking
3.3.6.2 The Daily Build/Test/Release & Milestone-based Synchronize & Stabilize Process 1 Advices for HDL Designers Who Want to from Migrate from Behavioral HDL to C without Pain 2 Open Discussion

day1 pm 1. C for HW Modeling & Verification ? Part II
1.1 C Design Flow for HW Modeling ? The Verification View
1.2 C for HW Modeling
1.2.1 C for Behavioral View Modeling: Imperative Vs Concurrent
1.2.2 C for Structural View Modeling
1.2.3 References, Pointers & Arrays for Constant, Register & Memory Modeling
1.2.4 Structures & Unions for Complex Memory Modeling
1.2.5 On Synthesis Pragma
1.3 Testbenches, Tracing & Debugging
1.4 Simulation Vs Code Coverage
1.5 C based Testbench Automation for Smart Verification: Deterministic Tests, Directed Random Tests & Trace-driven Tests
1.6. The Layered Testbench Architecture
1.7 Advanced Smart Verification Techniques based on C-level Modeling
1.8.1 Data Introspection: Static Extension Vs Dynamic Extension
1.8.2 Randomization Issues: Weighted Vs Constrained
1.8.3 Constraints Creation & Handling: Soft Vs Hard; Flat Vs Hierarchical 1 Tricks on Testbench Authoring& Design Debugging 2 Case Study (Part I): Modeling & Verify the Motion Compensation Algorithm in MPEG-I Application in 3 Open Discussion

day2 am 1. From C to Synthesizable HDL at RTL ? From Head to Toe
1.1 C Design for HW Modeling: The Synthesis View
1.2 Synthesizable Subset of HDL: Verilog Vs VHDL
1.3 Cycle-based Model Vs Discrete Event Model
1.4 RTL Essence Revisited 1.4.1 Controller & Datapath
1.4.2 Controller: Hardwired Vs. Programmable
1.4.3 FSM: Mealy Machine Vs. Moore Machine
1.4.4 Programmable Controller Design Issues
1.4.5 Datapath In Depth
1.5 Refine from C to Cycle-based C 1 Refine Cycle based C to Synthesizable RTL 2 Case Study (Part II): Synthesize & Verify C Model of the Motion Compensation Algorithm in MPEG-I Application - From Cycle-based C to Synthesizable HDL 3 Open Discussion

day2 pm 1. C for HW/SW Co-design of SoC ? an Introduction
1.1 IP-based SoC Design ? The Call for HW/SW Co-design
1.2 Computation Model: HW Vs SW
1.3 Communication Model: HW & SW
1.4 Instruction Set Architecture (ISA)
1.5 Customized RTOS, Compiler, Linker, Debugger & ISA Simulator for Customized ISA
1.6 C for Unified HW/SW Co-design
1.6.1 C for HW/SW Co-modeling 1 C for HW/SW Co-simulation 2 Open Discussion

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