Advanced IC Design and Software Engineering Training

EDA Flow (IC Design Process) Setup & Turning & Its A Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1 Opening Remark 2 From the State-Of-Practice to the State-Of-Art -IP based SoC Design under COT Flow

2.1 The SoC Design Challenges: Timing Closure, Signal Integrity, Performance Bottleneck & Low Power Requirement
2.2 The Problems with Traditional Synthesis: The Decoupling of Logic & Layout
2.3 Minor Improvements of Traditional Synthesis: Placement-knowledge Synthesis
2.4 Different Solution Planes Used by Synthesis and Placement & Routing
2.5 On IP based Design Reuse
2.6 The RTL to GDSII Flow for SoC Design 1 The Calling for a Good EDA Flow (IC Design Process) 2 The Essence of EDA Flow (IC Design Process)

3.1 Fundamental Jargons in IC Design Process ? Phases, Milestones, Buffer Time, Scheduling, Resource Allocation, Productivity, Performance
3.2 IC Design Artifacts: Specification, Source Code, Test Cases, Layout, Documentation, Manual, Guidelines, Standards & Templates
3.3 IC Design Processes: Heavyweight Methodology Vs Lightweight Methodology
3.4 Phases in IC Design Process: Initiating, Planning, Executing, Controlling and Closing
3.5 Key Objectives of IC Design Process Automation
3.5.1 Automate Tasks within the IC Design Process
3.5.2 Track & Manage the IC Design Process 1 Produce a Dependable, Repeatable and Effective IC Design Process 2 Introduction to Tcl for Automating EDA Flow

4.1 Control Flow in Tcl
4.2 Advanced String Processing Features in Tcl
4.3 Networking Capability in Tcl5. Open Discussion

1st Day(1:00PM ~ 4:00PM) 1. EDA Flow Set-up In Depth
1.1 The Choices of IC Design Methodology: ASIC Vs COT, Flat Vs Hierarchical, IP based vs Non-IP based
1.2 The Choices of Tools & Vendors
1.2.1 Point Tools Vs Total Solutions (Frameworks); COTS Vs In-house, Desktop-based Vs Network-based
1.2.2 Current Available EDA Flow Automation Tools: Tool Launchers, Tool Sequencers & Flow Sequencers
1.3 EDA Flow Standards, Rules, Guidelines & Templates
1.4 Detailed Steps in EDA Flow Setup
1.4.1 Requirement Elicitation & Analysis
1.4.2 EDA Tools Evaluation & Analysis: Front-end Vs Backend
1.4.3 Design Artifacts Management: Configuration Management & Quality Assurance
1.5 Key Elements for EDA Flow Success
1.5.1 Silicon Proven Libraries: Macro, IP, I/O, Digital Logic & Analog Cells
1.5.2 Silicon Proven Design Flows: Tools & The Integrations of Tools
1.5.3 Silicon Proven Process & Fabrication 1 Production Proven Testing & Assembly 2 Case Study I: Migrating from Reverse Engineering Flow to ASIC Flow in a Well Established Local IC Design House 3 Open Discussion

2nd Day (9:00AM ~ 12:00AM) 1. EDA Flow Turning In Depth
1.1 Identifying the Flow Bottleneck through Design Data Gathering & Analysis 1 Fixing the Flow Bottleneck 2 Specific Issues in EDA Flow Setup & Turning

2.1 From Reverse Engineering Flow to ASIC Flow
2.2 From FPGA Flow to ASIC Flow
2.3 From ASIC Flow to SoC Flow ? Internal Efforts
2.3.1 Investing on Design Team: The Augment of Backend Design Capability
2.3.2 Investing on EDA Tools: The Augment of Backend Design Capability
2.3.3 Investing on Post Silicon Verification Capability
2.3.4 Investing on Production Testing Capability
2.4 From ASIC Flow to SoC Flow ? External Co-operations
2.4.1 IP Vendor Cooperation ? IP Models
2.4.2 Foundry Cooperation ? Process Models & Design Models
2.4.3 Foundry Checklist for COT Flow Validation: Construction Analysis, Wafer-level Reliability, Packaged Product Qualification, Chip Performance Measurement
2.4.4 Test Vendor Cooperation
2.4.5 Assembly Vendor Cooperation
3. Open Discussion

2nd Day(1:00PM ~ 4:00PM) 1. Automating EDA Flow Setup & Turning through Tcl Scripting
1.1 Why EDA Vendor Provided Scripts Are Not Enough?
1.2 Define & Customize Your EDA Flow before Scripting for EDA Flow Automation 1 Effective & Efficient Scripting for EDA Flow Automation 2 Case Study II: Build & Automate COT Flow in a Silicon Valley Startup 3 Open Discussion

Back to Home Page