Advanced IC Design and Software Engineering Training

FPGA based Custom Prototyping in Accelerating Your SOC Desig Program Agenda (Subject to Change without Notice) Date Agenda

1st Day 9:00AM ~ 12:00AM 1.Opening Remark

3. Issues in Million-Gates SoC/ASIC Design
3.1 On Design Frontier
3.1.1 ASIC Flow Vs COT Flow
3.1.2 Gate-level Sign-off Vs RTL Sign-off
3.1.3 Flat Design Vs Hierarchical Design
3.2 Million-Gates SoC/ASIC Design Challenges
3.2.1 The Product Definition Challenges
3.2.2 The Design & Development Challenges
3.2.3 The Post-silicon Challenges
3.2.4 The Production Challenges
3.2.5 The Verification Challenges
3.3 Issues in Design Verification
3.3.1 Simulation Vs Prototyping ? Where the Simulation Performance Bottleneck Comes?
3.3.2 RTL Prototyping: Real Prototyping Vs Virtual Prototyping
3.3.3 Modular Prototyping (FPIC based Vs Bypass Transistor based) Vs Custom Prototyping (Pre-tapeout Verification Vs Post-silicon/Pre-production Validation)
3.3.4 Why Accelerations & Emulation (Modular Prototyping) Are Too Much for Million-Gates SoC/ASIC?
3.5 Why FPGA Custom Prototyping Is Your Verification Solution?3.5.1 1,000 to 100,000X Performance Gain over HDL simulation
3.5.2 For Early Technology Demo & Early SW Development Kick-off
3.5.3 HW Vehicle for Development of HW/SW for Final Product
3.5.4 Verification of Time Critical Functions and/or IP
3.5.5 Analysis of New Feature Sets
3.5.6 Testing & Optimizing Algorithms
3.5.7 Investigation of SW/HW Tradeoff
3.5.8 Allow Late Stage Design Changes
3.5.9 Make Debugging & Probing Flexible 1 Avoid or Reduce Silicon Re-spin & NRE Cost 2 Open Discussion

1st Day1:00PM ~ 4:00PM 1. FPGA Architecture & Methodology In Depth
1.1 FPGA Architecture Suitable for Rapid Prototyping
1.1.1 Related Xilinx Architecture In Depth
1.1.2 Related Altera Architecture In Depth
1.2 FPGA Architecture for IP based Design Reuse
1.2.1 Altera‘s IP based FPGA Design Platform & Methodology
1.2.2 Xilinx‘s IP based FPGA Design Platform & Methodology 1 From Field Programmable Computing to Reconfigurable Computing Hope or Hype? 2 Advanced FPGA Design Tips

2.1 Key Difference between FPGA Design & SOC/ASIC Design
2.1.1 On Architecture Differences
2.1.2 NRE Cost
2.1.3 On Timing & STA Issues
2.1.4 On Clock Skew & Power Issues
2.2 Synchronous Design Techniques Minimizing Timing Issues: from Gated Clock to Global Clock
2.3 Exercise Care with Latches (if Necessary) & FSMs
2.4 Keep Track of Clocks, Resets and Other Timing Issues: Multiple Clock Domains, Asynchronous Reset Vs Synchronous Reset, Clock Management, PLL
2.5 Special Issues Handling
2.5.1 Running Out of Clock Buffers
2.5.2 Inadequate Verification with Inappropriate Stimulus
2.5.3 The Verification by Testing Pitfall
2.5.4 Risks in Not Performing Worst Case Timing Analysis

3. Case Study I: How to Set Up FPGA Prototyping Flow for SOC/ASIC Design?

4. Open Discussion

2nd Day 9:00AM ~ 12:00AM 1. FPGA Prototyping Flow for SOC/ASIC Design
1.1 Design Capture ? Visual Entry Vs. Text-based Entry
1.2 Timing Constraints Specification ? What Differs between FPGA & SOC/ASIC
1.3 Functional & Timing Simulation
1.4 Static Timing Analysis Can Be Eliminated
1.5 Floorplanning, Placement & Routing
1.6 Special Handling on Memories & IP Blocks such as CPU
1.7 Why Is It Important to Match FPGA Design Flow with SOC/ASIC Design Flow?
1.8 Custom Prototyping Boards Vs Commercial Prototyping Boards & Their Comparison
1.9 Commercial Vs Commercial Prototyping EDA Tools
1.10 Risks in Using FPGA for SOC/ASIC Prototyping

2. Case Study II: FPGA Prototyping for a Telecommunication SoC

3. Open Discussion

2nd Day 1:00PM ~ 4:00PM 1. FPGA Prototyping Design Methodology for SOC/ASIC Design
1.1 Design Initiation: Requirements, Feasibility Study, Risk Analysis
1.2 Initial Analysis: Specification, Development Plan
1.3 Architectural Design
1.4 Detailed Design
1.5 Floorplanning, Placement & Routing
1.6 Programming, Debugging & Testing
1.7 Documentation & Review 1 Key Differences between FPGA Design & SOC/ASIC Design & How to Accomadate It 2 Different Scenarios of FPGA Prototyping In Depth

2.1 Prototyping for RTL Golden Sign-off ? The Regression Issues
2.2 Prototyping for Pre-tapeout Verification ? The Chip Verification Environment
2.3 Post-silicon/Pre-production Validation ? The System Debug Architecture

3. Open Discussion

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