Advanced IC Design and Software Engineering Training

HW/SW Co-Design & Co-Simulation for Platform-based SoC Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1 Opening Remark 2 Why Platform-based SoC & Why HW/SW Co-design?

2.1 Design Flows at a Glance: FPGA, ASIC & COT
2.2 The Time-To-Market, Cost, Performance & Power Challenge in SoC based Products
2.3 The Timing Convergence, Signal Integrity & Design Process Challenge in SoC Design
2.4 Gate-level Sign-off Vs RTL Sign-off
2.5 Timing-driven Synthesis Vs Timing-frozen Synthesis
2.6 Block based Design Vs. Platform based Design
2.7 Sequential HW/SW Design Vs HW/SDW Co-design
2.8 Design Reuse: IP-based HW Reuse Vs Component-based SW Reuse 1 The Calling for HW/SW Co-design of Platform-based SoC 2 High-Level Language based HW/SW Co-design - From Algorithm to System

3.1 Y Chart & Design Space Exploration
3.2 The Gap between Algorithm & Architecture
3.3 Computation Models, Communication Models & Modeling Languages
3.4 Block based Design Vs. Platform based Design
3.5 HW/SW Partitioning from System Perspective
3.6 System Level Modeling Challenges in SoC Design
3.7 Algorithm Modeling, Optimization & Partitioning
3.8 MatLab, Java/C/C++, Hardware-C/SystemC for System-level Design 1 An Unique Perspective on SystemC 2 Open Discussion

1st Day (1:00PM 4:00PM) 1.The HW View of HW/SW Co-design ? IP based SoC Integration
1.1 The Calling for Reusable HW Architecture in HW/SW Co-design
1.2 On Evaluating & Selecting Hard IP, Firm IP and Soft IP
1.3 An Unique Perspective on ARM Vs MIPS
1.4 IP Integration Flows: Soft IP, Firm IP & Hard IP
1.5 The IP based SoC Integration Challenge and Best Practices 1 The Industrial Efforts on Automating IP based SoC Integration Process 2 The SW View of HW/SW Co-design I - Retargetable Compiler & Debugger

2.1 The Calling for Retargetable SW Architecture in HW/SW Co-design
2.2 Compiler & Debugger for SoC
2.3 The Retargetable Compiler & Debugger
2.4 GNU Retargtable Compiler gcc In Depth 1 GNU Retargtable Debugger gdb & Its Remote Client In Depth 2 Demo : Customizing gcc, gdb & new_lib for ARM-thumb ISA on Linux

3. Open Discussion

2nd Day (9:00AM ~ 12:00AM) 1. The SW View of HW/SW Co-design II - Reconfigurable RTOS
1.1The Monolithic OS, Layer OS & Microkernel based OS
1.2Non-preemptive, Semi-preemptive & Preemptive Scheduling
1.3Priority based Vs Round Robin Scheduling
1.4Priority Inversion & Its Solution
1.5RTOS for SoC
1.6eCos In Depth

2 Demo: Customizing eCos for ARM-thumb ISA on Linux

3 Open Discussion

2nd Day (1:00PM ~ 4:00PM) 1.Simulation View of HW/SW Co-design
1.1Bus Functional Model Vs Cycle-based Model
1.2HW/SW Co-Simulation In Depth: From HW Architecture Point of View
1.3HW/SW Co-Simulation In Depth: From SW Architecture Point of View
1.4SoC‘s Debug Architecture: JTAG, BIST among others
1.5A Comparison of Commercial HW/SW Co-Simulation/ Co-Validation Tools

2.Design Process View of HW/SW Co-design
2.1The Design Success Triangle: Process, People & Technology
2.2Design Artifacts Tracability & In-house Tool Demo
2.3Version Control In Depth & CVS Introduction
2.4Change Request Management & IssueView Introduction
2.5On Automatic Regression Test & Quality of Result (QoR) Test
2.6Multi-team/Multi-site Design Activity & ClearCase, LSF Introduction
2.7Design Process Setup, Validation, Measurement & Optimization ? Do We Need IC Design CMM?

3. Open Discussion

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