Advanced IC Design and Software Engineering Training

HW/SW Co-Design for SoC in SystemC Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~ 12:00AM) 1 Opening Remark 2 COT (Customer Owned Tooling) Flow for Low Power SoC

2.1 Design Flows: FPGA, ASIC & COT
2.2 Libraries & IP in COT Flow: Live By the Model, Die By the Model
2.3 From Algorithm to System & From RTL to GDSII
2.4 Migrating from ASIC Flow to COT Flow
2.5 COT Flow Setup, Validation & Optimization
2.6 Product Definition, Design & Development, Post Silicon & Production of in COT Flow
2.7 The Timing Convergence, Signal Integrity & Design Process Challenge in COT Flow
2.8 Industry-strength COT Flow for SoC Design at a Glances 1 2 Cents for COT Flow for SoC Design 2 From Algorithm to System

3.1 The Gap between Algorithm & Architecture
3.2 Computation Models, Communication Models & Modeling Languages
3.3 Block based Design Vs. Platform based Design
3.4 SoC Design Flow: Top-down, Bottom-up & Meet-in-the-Middle
3.5 IP based SoC Design
3.6 HW/SW Co-design of SoC 1 Design Process Issues of SoC 2 High-Level Language based System-level Synthesis

4.1 System Level Modeling Challenges in SoC Design
4.2 Algorithm Modeling, Optimization & Partitioning
4.3 System-level Co-design, Co-simulation and Co-verification 1 MatLab/SDL, Java/C/C++, Hardware-C/SpecC/SystemC for System-level Design 2 Open Discussion

1st Day (1:00PM 4:00PM) 1.IP based SoC HW/SW Co-design Methodology

2.1 Hard IP, Firm IP and Soft IP
2.2 IP Characterization, Encryption, Selection and Integration
2.3 IP Reusability and Integration Challenge
2.4 HW/SW Co-design & Co-verification
2.5 The Role of SW/FW in SoC Design
2.6 The Key Difference of ASIC Flow & SoC Flow
2.7 The IP based SoC Integration Challenge and Best Practices
2.8 Why SoC Is NOT the State-Of-The-Art?

3. SystemC In Depth ? Part I
3.1 The History of SystemC
3.2 Computation Models in SystemC
3.3 Communication Models in SystemC
3.4 Abstraction Levels in SystemC
3.5 HW View Vs. SW View in SystemC
3.6 Simulation View Vs. Synthesis View in SystemC
3.7 Synthesizable Subset of SystemC 1 Design Flow Issues in Using SystemC 2 Case Study I: Designing an DCT Chip in SystemC 3 Open Discussion

2nd Day (9:00AM ~ 12:00AM) 1.SystemC In Depth ? Part II
1.1 Modules & Hierarchy in System C
1.2 Process in SystemC
1.3 Ports & Signals in SystemC
1.4 Data Types in SystemC
1.5 How to Approximate Floating Point Data Type with Fixed Point Data Type with SystemC?
1.6 Modeling HW in SystemC
1.7 Modeling SW in SystemC
1.8 HW/SW Co-design with SystemC 1 Introduction to Synopsys Cocentric Tool Suites 2 Case Study II: Design a Pipelining FFT (Fast Fourier Transform) Chip in SystemC 3 Open Discussion

2nd Day (1:00PM ~ 4:00PM) 1ㄝSystemC In Depth 每 Part II
1.1 Refinement methodologies
1.1.1 Wrapping and merging
1.1.2 Using adapters
1.2 Data types
1.3 RTL Modeling
1.3.1 Hardware ports
1.3.2 Signals
1.3.3 Module connection
1.3.4 Clock generation
1.3.5 Registered logic
1.3.6 Combinational logic
1.4 Data structure and navigation
1.4.1 Object and simulation context classes
1.4.2 Attributes
1.4.3 Modules and ports in detail
1.5 Debug and Tracing
1.5.1 Native debug
1.5.2 Assertions
1.5.3 sc_trace features 1 Tracing methodologies 2 Open Discussion

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