Issues in Designing Mixed-Signal Designs Program Agenda (Subject to Change without Notice) Schedule Agenda
1st Day (9:00AM~ Noon)
1 Opening Remark
2 The Paradigm Shifting from Old SoC to New SoC
2.1 Categories of SoC: Heterogeneous Integration, High Performance, Low Cost/Low Power
2.2 IP-based Design Reuse Methodology Revisited
2.3 The Old SoC: Embedded DRAM SoC Powered by MPU
2.4 The New SoC: Mixed Signal, Embedded DRAM SoC Powered by MPU
2.5 The New SoC Design Constraints: Performance, Cost, Power, Reliability & Yield
2.6 The New SoC Design Challenges: The Gap between Design Technology & Manufacture Technology
2.7 Basic Building Blocks in Mixed Signal Design: LNA, VCO, PLL, PA, ADC & DAC
2.8 An Overview of Leading Analog IPs
2.8.1 DAC IP: Current Steering & Resistor Ladder
2.8.2 ADC IP: Algorithmic, Sigma Delta, Pipeline
1 Programmable PLL IP
2 VDSM CMOS Technology for Mixed-Signal SoC Revisited
3.1 Suitability of CMOS Technology
3.2 MOSFET Scaling Technology
3.3 Local & Global Interconnect Modeling: Resistance, Capacitance & Inductance
3.4 Driver Models: Resistance Shielding & Effective Capacitance
3.5 Problems & Solutions Regarding Long Wires
3.6 Reliability Issues: Noise & Electromigration Analysis & Optimization
3.7 Layout Issues: Antenna Effect & Substrate Coupling
1 Issues on Integrating Digital Blocks & Analog Blocks within a Single Process
2 Open Discussion
1st Day (1:00PM~4:00PM)
1.Analog Building Block Operational Amplifiers In Depth
1.1Design Constraints: Gain, Setting Time, Energy Efficiency & Yield
1.2Operational Amplifier Design in Low Voltage Processes
1.3Basic Op Amp Design
1.4Advanced Op Amp Design
1.5Emerging Amplifier Design Strategies
2.Analog Building Block ADC In Depth
2.1Design Constraints: Speed, Resolution, Energy Efficiency & Yield
2.2Oversampled/Delta-Sigma ADC
2.3Flash ADC
2.4Pipelined ADC
3. Open Discussion
2nd Day
(9:00AM~ Noon)
1 Analog Building Block PLL/DLL In Depth
1.1Why On-Chip PLL/DLL Is Necessary for SoC?
1.2The Principle behind PLLs & DLLs
1.3How PLLs Differs DLLs
1.4PLL Architectures: Phase Detectors, Charge Pump & VCO
1.5DLL Specific Issues
1.6Advanced PLL Architectures
1.7PLL/DLL Circuits at a Glance
1.8PLL/DLL Applications: Frequency Multiplication & Synthesis, Skew Reduction & Jitter Reduction
2 High Performance Power Distribution for Reliability
2.1 Power Grid Modeling
2.2 Power Grid Analysis
2.3 Power Grid Design & Optimization
1 Forget About Power Routing In Mixed-Signal SoC Jungle
2 Mixed-Signal SoC Front-end Issues: Specification & Synthesis Issues
3.1 Hierarchical Mixed-Signal SoC Design Methodology: Top-down, Bottom-Up & Meet-In-the-Middle
3.2 From Mixed-Signal Design to Mixed-Signal Synthesis
3.3 Analog Synthesis Approaches: Knowledge (Rule) based Vs Mathematical (Equation) based
3.4 Behavioral Modeling & Synthesis of Mixed-Signal SoC Design
3.5 Introduction to Verilog-AMS & VHDL-AMS
1 Front-end Optimization Techniques In Depth
2 Open Discussion
2nd Day (1:00PM~4:00PM)
1. Mixed-Signal SoC Verification Issues: Mixed-Signal Simulation
1.1 Verification: Static Timing Analysis Vs Dynamic Simulation
1.2 Dynamic Simulation: Cycle-based, Discrete-Event, Switch-level & Tra nsistor-level
1.3 Dynamic Simulation: Digital Vs Analog
1.4 Mixed-Signal Simulation: Combining Digital Simulation with Analog Simulation
1 On How to Speed-Up Mixed-Signal Simulation beyond EDA ToolĄŽs Capability
2 Mixed-Signal SoC Backend-end Issues
2.1 Library Building & Circuit Design ? High Quality Wine Came from First Class Grapes
2.2 Floorplanning Issues: Building Block Style ? a Mix of Standard Cells & Macros
2.3 Placement Issues: Automatic Placement & Manual Placement
2.4 Routing Issues: Routability Driven & Reliability-Aware
2.5 Special Routings: Power Routing Revisited & Clock Routing
2.6 From Analog Layout Design to Analog Layout Synthesis
2.7 Analog Layout Synthesis Approaches: Cell Layout Vs System Assembly
2.8 Analog Layout Synthesis Goals: Quantitative Optimization Vs Performance Optimization
1 Back-end Optimization Techniques In Depth
2 Mixed-Signal SoC Verification Issues: Mixed-Signal Testing
3.1 Metrics & Techniques of Mixed-Signal Testing
3.2 DFT for Analog Blocks
3.3 BIST for Analog Blocks
3.4 Analog Parameter Testing Using Digital Sampling Techniques
3.5 Delta-Sigma Modulation Techniques for Mixed-Signal Testing Applications
1 Introduction to IEEE P1149.4 - Mixed-Signal Extension of JTAG
2 Case Study: Design a Mixed-Signal Soc for Wireless Application
3 Open Discussion
© Copyright 2004-2007 Hometown Innovation Automation Inc
All Rights Reserved
Back to Home Page