Advanced IC Design and Software Engineering Training

Key Issues in Reliable High Speed PCB Design Program Agenda (Subject to Change without Notice) Date Agenda

1st Day (9:00AM ~4:00PM) 1 Opening Remark 2 PCB Design Methodology at Glances

2.1 Popular PCB Design Flows 1 Leading PCB Design Tools 2.3 The Challenges on PCB Designs: Performance, Power & Reliability 2 Crosstalk Issues of Advanced PCB Design

3.1 Mutual Inductance and Mutual Capacitance
3.2 Inductance and Capacitance Matrix
3.3Field Simulators
3.4 Crosstalk Induced Noise
3.5 Simulating Crosstalk Using Equivalent Circuit Models
3.6 Crosstalk-Induced Flight Time and Signal Integrity Variations
3.6.1 Effect of Switching Patterns on Transmission Line Performance
3.6.2 Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Model
3.7 Crosstalk Trends
3.8 Termination of Odd- & Even-Mode Transmission Line Pairs
3.9 Signal Distribution Issues
3.10 Net Layout Issues 1 Rules of Thumb On Minimization of Crosstalk 2 EMI Issues of Advanced PCB Design

4.1 VIA Considerations
4.2 Connector Considerations
4.2.1 Shut Capacitance
4.2.2 Connector Crosstalk
4.2.3 Effects Of Inductively Coupled Connector Pin Fields
4.2.4 Connector Design Guidelines
4.3 Grounding Considerations
4.4 Power Distribution
4.5 The Basics of Interference 1 Rules of Thumb on Minimizing EMI 2 Performance Issues of Advanced PCB Design 5.1 Setup Time Vs Hold Time ? Speed Constraint Vs Functional Constraint

5.2 Common Clock Timing, Source Synchronous Timing & Alternative Source Synchronous Timing
5.3 Minimizing the Effect of Clock Jitter & Clock Skew: Clock Network Design Vs PLL
5.4 Reduce the Delay of Logic Path: Pipelining Vs Concurrent
5.5 On Choosing High Speed Chips
5.6 High Performance Bus Architecture
5.7 High Speed Memory Architecture
5.8 Rules of Thumb on High Speed PCB Design6. Open Discussion

2nd Day (1:00PM ~ 4:00PM) 1. Chip Packages Issues of Advanced PCB Design 1.1 Common Types of Packages
1.1.1 Attachment of the Die to the Package
1.1.2 Routing of the Signals on the Package
1.1.3 Attachment of the Package to the Board 1.2 Package Modeling Issues
1.3 Effects of a Package
1.3.1 Point-to-Point Bus Topology
1.3.2 Mutidrop or Daisy Chain Topologies
1.3.3 Long Package Stub Effect
1.3.4 Widely Spaced Short Package Stub Effect
1.3.5 Distributed Capacitive Loading on a Bus
1.3.6 Optimal Pin-Outs 1 Rules of Thumb for Optimal Package Design 2 Reliability Issues of Advanced PCB Designs

2.1 Why Reliability & Performance?
2.2 Reliability Theory
2.2.1 Reliability Mathematics
2.2.2 Hazard Rate Curve
2.2.3 Common Failure Distributions in Reliability
2.2.4 Sample Use of Time-to-Failure Distributions
2.3 Effect of Environment on PCB Reliability
2.3.1 Temperature
2.3.2 Vibration
2.3.3 Mechanical Shock
2.3.4 Moisture
2.3.5 Ionic Contamination
2.4 PCB Stress Analysis
2.4.1 Thermal Analysis
2.4.2 Vibration Analysis
2.5 PCB Failure Mechanisms and Models
2.5.1 Damage Models and Metrics
2.5.2 Permanent Interconnects
2.5.3 PCB Metalization
2.5.4 Contact and Connector Failures 1 Summary of PCB Failure Mechanism and Models 2 Case Studies

3.1 Case Study 1: Military-Designed Circuit Board
3.1.1 Description of the PCBs and Environment
3.1.2 Vibration Analysis
3.1.3 Thermal Analysis
3.1.4 Failure Mechanism Analysis
3.1.5 Experimental Test Results
3.1.6 Cost Saving from this PoF Analysis
3.2 Case Study 2: VME Processor Circuit Card Assembly
3.2.1 Description of the PCB and Environment
3.2.2 Thermal Analysis
3.2.3 Vibrational Analysis
3.2.4 Failure Mechanism Analysis
3.2.5 Analysis Conclusion
3.3 Case Study 3: Circuit Card Assembly in a Military Environment
3.3.1 Vibration Analysis
3.3.2 Thermal Analysis
3.3.3 Failure Analysis 1 Analysis Conclusions 2 Open Discussion

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