Advanced IC Design and Software Engineering Training

Low Power Design Techniques for High Performance CMOS IC Program Agenda (Subject to Change without Notice) Date Agenda

1.Opening Remark High Speed Design Techniques Revisited
2.1 What Is Speed ? Clock Frequency or Execution Time?
2.2 The High Speed & High Band
2.3Algorithmic Design & Optimization for High Speed ? Profiling Your Algorithmic Code
2.3.1 On Floating Point to Fixed Point Approximation
2.3.2 On HW/SW Partitioning and/or Cold HW/Hot HW Partitioning
2.4 Speed Up Your Design through Parallelism
2.5 Setup Time Constraint Vs Hold Time Constraint ? Speed Constraint Vs Functional Constraint
2.6 High Speed Library Design ? Sequential Cells, Combinational Cells & Datapath Blocks
2.7 Reducing Combinational Path Delay Through
2.7.1 Pipelining ?RTL Vs Gate-level
2.7.2 Logic Restructuring
2.8 Reducing Clock Skew & Clock Jitter Through
2.8.1 On-chip DLL or On-chip PLL
2.8.2 Custom Clock Tree
2.9 On-chip Memory: SRAM, DRAM & Flash
2.10 High Performance Bus Architecture
2.10.1 Introduction to Rambus 1 Introduction to AMBA 2 Low Power for High Speed Design Overview

3.1 Minimize Your Energy Delay Product for Speed/Power Trade-off
3.2 The Sources of Power Consumption ?Switching Power, Standby Current Induced Power, Leakage Power & Short-circuit Current Induced Power
3.3 Low Power Design Space: Voltage, Physcial Capacitance, Switching Activity & SW Related
3.4 Making Design Trade-offs among Performance, Power, Area & Reliability
3.5 Process/Voltage Scaling Techniques for Low Power (Not Fully Addressed in This Lecture)
3.6 Impact of Packaging on Low Power (Not Fully Addressed in This Lecture)
3.7 Reliability Issues in Low Power Design (Not Fully Addressed in This Lecture): Soft Failure Vs Hard Failure
3.8 Techniques for Leakage Power Reduction (Not Fully Addressed in This Lecture)
3.9 The Emerging Asynchronous Design Methodology for Low Power
3.10 Low Power IP Architecture at a Glance: ARM Vs MIPS 1 Low Power Design Flows at a Glance 2 Open Discussion

day1 pm 1. Low Power Design for High Speed through Switching Activity Minimization
1.1 Power Estimation through Switching Activity Estimation
1.1.1Factors May Have Effects on the Accuracy of Switching Activity Estimation: Input Pattern Dependence, Delay Model, Logic Function, Circuit Style & Circuit Topology
1.1.2 Switching Activity Estimation Techniques: Simulation-based Approach Vs Non-Simulation-based Approach
1.2 Algorithmic Code Profiling in Minimizing Switching Activity
1.3 Micro-architecture Design in Minimizing Switching Activity
1.3.1 Bus Architecture
1.3.2 Memory Hierarchy
1.3.3 The Trade-off between Parallelism & Pipelining
1.3.4 The Choice of Clocking Scheme
1.3.5 When Will a Custom Power Management Unit (PMM) Be Necessary?
1.4 Operation Isolation in Minimizing Switching Activity
1.5 State Encoding for Low Power
1.6 Clock Gating: Gated Clock Vs Clock Enable in Minimizing Switching Activity
1.7 Gate Sizing in Minimizing Switching Activity: Convert Speed to Low Power
1.8 Technology Mapping in Minimizing Switching Activity
1.9 Custom Datapath Design in Minimizing Switching Activity: Path Balancing among Others
1.10 Relaxation based Switching Activity Minimization Speed & Area Penalty Consideration 1 Comparison of Related Commercial Low Power Design Tools 2 Case Study I：Low Power Design of a Memory Controller for Rambus based Bus Architecture 3 Open Discussion

day2 am 1. Low Power Design for High Speed through Physical Capacitance Minimization
1.1 Power Estimation through Physical Capacitance Estimation
1.1.1The Impact of Parasitic RC Extraction Accuracy of Physical Capacitance Estimation
1.1.2 The Impact of Delay Model Accuracy on the Efficiency of Physical Capacitance Estimation
1.3 Library Design and/or Optimization for Physical Capacitance Minimization
1.4 Migrating from Gate-centric Design to Interconnect-centric Design for Physical Capacitance Minimization
1.5 Floorplanning, In-Placement Optimization for Physical Capacitance Minimization
1.6 Transistor Sizing for Physical Capacitance Minimization
1.7 Custom Clock Distribution Network Design & Optimization for Physical Capacitance Minimization
1.8 Custom Power Distribution Network Design & Optimization for Physical Capacitance Minimization
1.9 Custom Memory Block Design for Physical Capacitance Minimization
1.10 Relaxation based Physical Capacitance Minimization with Speed & Area Penalty Consideration
1.11Cmparison of Related Commercial Low Power Design Tools 1 Introduction to a Custom Power Optimization Flow Derived from Traditional Timing-driven Synthesis Flow 2 Case Study II: The ARM Approach on Low Power RISC IP/Core Design3. Open Discussion

day2 pm 1. Low Power Design for High Speed through Power-driven SW Optimization
1.1 Why SW Related Power Consumption Becomes Significant?
1.2 Instruction Set Architecture (ISA) Issues for Low Power
1.3 Compiler Technology for Low Power
1.3.1 Instruction Scheduling for Low Power
1.3.2 Register Minimization for Low Power through Memory Spill Reduction
1.3.3 Special Techniques on Low Power Optimization: Pruning, in-lining & Loop Unrolling
1.3.4 The Trade-off among Code Size, Code Speed & Code Power Consumption
1.4 RTOS Technology for Low Power
1.4.1 Managing Your IC Power Consumption with RTOS
1.4.2 The Emergence of Low Power Kernel API 1 The Road towards HW/SW Co-design for Low Power 2 Case Study III: Measurement of SW Execution Power Consumption on StrongArm 3 Open Discussio

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