Migrating from ASIC Flow to COT Flow
Program Agenda (Subject to Change without Notice)
1st Day (9:00AM ~ 12:00AM)
1 Opening Remark
2 From the State-Of-Practice to the State-Of-Art -IP based SoC Design under COT Flow
2.1 The SoC Design Challenges: Timing Closure, Signal Integrity, Performance Bottleneck & Low Power Requirement
2.2 The Problems with Traditional Synthesis: The Decoupling of Logic & Layout
2.3 Minor Improvements of Traditional Synthesis: Placement-knowledge Synthesis
2.4 Different Solution Planes Used by Synthesis and Placement & Routing
2.5 On IP based Design Reuse
2.6 The RTL to GDSII Flow for SoC Design
1 The Calling for a Good EDA Flow (IC Design Process)
2 The Essence of EDA Flow in IC Design Process
3.1 Fundamental Jargons in IC Design Process ：C Phases, Milestones, Buffer Time, Scheduling, Resource Allocation, Productivity, Performance
3.2 IC Design Artifacts: Specification, Source Code, Test Cases, Layout, Documentation, Manual, Guidelines, Standards & Templates
3.3 IC Design Processes: Heavyweight Methodology Vs Lightweight Methodology
3.4 Phases in IC Design Process: Initiating, Planning, Executing, Controlling and Closing
3.5 Key Objectives of IC Design Process Automation
3.5.1 Automate Tasks within the IC Design Process
3.5.2 Track & Manage the IC Design Process
3.5.3 Produce a Dependable, Repeatable and Effective IC Design Process
1st Day(1:00PM ~ 4:00PM)
1. EDA Flow Set-up In Depth
1.1 The Choices of IC Design Methodology: ASIC Vs COT, Flat Vs Hierarchical, IP based vs Non-IP based
1.2 The Choices of Tools & Vendors
1.2.1 Point Tools Vs Total Solutions (Frameworks); COTS Vs In-house, Desktop-based Vs Network-based
1.2.2Current Available EDA Flow Automation Tools: Tool Launchers, Tool Sequencers & Flow Sequencers
1.3 EDA Flow Standards, Rules, Guidelines & Templates
1.4 Detailed Steps in EDA Flow Setup
1.4.1Requirement Elicitation & Analysis
1.4.2EDA Tools Evaluation & Analysis: Front-end Vs Backend
1.4.3 Design Artifacts Management: Configuration Management & Quality Assurance
1.5 Key Elements for EDA Flow Success
1.5.1 Silicon Proven Libraries: Macro, IP, I/O, Digital Logic & Analog Cells
1.5.2 Silicon Proven Design Flows: Tools & The Integrations of Tools
1.5.3 Silicon Proven Process & Fabrication
1 Production Proven Testing & Assembly
2 Open Discussion
2nd Day (9:00AM ~ 12:00AM)
1. What Differs in Front-tend Side? ASIC Flow Vs. COT Flow
1.1 The Calling for Cost Reduction, Timing Closure & Signal Integrity
1.2 Difference on Technical Issues between ASIC Flow & COT Flow
1.3 Difference on Business Model Issue between ASIC Flow & COT Flow
1.4 The Ownership of Backend Design Does Not Necessarily Mean High Performance
1 RTL Prototyping, Design Planning & RTL Floor planning
2 Backend Side of COT Flow
2.1 Pre-physical Design Analysis: Code Coverage, Testability, Power, Performance & Code Purification
2.2 Floor planning
2.3 Clock & Power
2.4 Placement
2.5 DFT
2.6 Routing
2.7 Timing Closure & Signal Integrity Closure
1 Custom Design for High Performance
2 Open Discussion
2nd Day (1:00PM ~ 4:00PM)
1. Key Issues in COT Flow Success
1.1 Identifying the Flow Bottleneck through Design Data Gathering & Analysis
1.2 Production Aspects of COT Flow
1.3 Migrating from ASIC Flow to COT Flow ：C Internal Efforts
1.3.1 Investing on Design Team: The Augment of Backend Design Capability
1.3.2 Investing on EDA Tools: The Augment of Backend Design Capability
1.3.3 Investing on Post Silicon Verification Capability
1.3.4 Investing on Production Testing Capability
1.4 Migrating from ASIC Flow to COT Flow ：C External Co-operations
1.4.1 IP Vendor Cooperation ：C IP Models
1.4.2 Foundry Cooperation ：C Process Models & Design Models
1.4.3 Foundry Checklist for COT Flow Validation: Construction Analysis, Wafer-level Reliability, Packaged Product Qualification, Chip Performance Measurement & Other Considerations
1.6.1 Test Vendor Cooperation
1 Assembly Vendor Cooperation
2 Key Elements for COT Flow Success
2.1Silicon Proven Libraries: IP, I/O, Digital Logic & Analog
2.2 Silicon Proven Design Flows: Tools & The Integrations of Tools
1 Silicon Proven Process & Fabrication 2.4Production Proven Testing & Assembly
2 Open Discussion
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