From ASIC Design to Structured ASIC Design
1.1 Why SoC Cannot Solve Problems that both ASIC and FPGA Cannot Solve: costTTM, Capacity, Performance, and Power & IP Reuse?
1.2 The Gap between FPGA & ASIC
1.3 Structured ASIC¡®s for Mid-Volume Designs
1.4 The Similarity & Difference between Structured ASIC Design & FPGA Design
2 Structured ASIC Properties
2 Low NRE cost
2.2 High performance
2.3 Low power consumption
2.4 Less Complex Manufacture Process
2.5 Shorter TTM
3 Structured ASIC Architecture
3.1.1 Structured Elements
3.1.2 Array of Structured Elements
3.2 The Granularity of Architecture: Fine Granularity Vs Medium Granularity
4 Structured ASIC Design Flow
4.2 Logical synthesis: Logic Optimization & Technology Mapping
4.3 DFT
4.4 CTS
4.5 Physical Synthesis: Placement & Routing
4.6 ASIC Flow Vs Structured ASIC Flow
4.7 FPGA Flow Vs Structured ASIC Flow
4.8 The Impact of Architecture Quality on Design Flow
4.9 The Impact of Library Quality on Design Flow
4.10 Supports from EDA Tool Vendors
4.11 Supports from FAB
5 Issues on Migrating from ASIC Design Structured ASIC Design & a Case Study
6 Issues on Migrating from SoC Design Structured ASIC Design & a Case Study
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