Frontier Journal
Exclusive Frontier Coverage on System Design
Vol. 3 No. 5 May 2006
GUEST EDITORIAL - Is Hardware Innovation Over? - MIT
Is Hardware Innovation Over? Professor Arvind, IEEE Fellow Johnson Professor of Computer Science and Engineering, MIT
With
the increasing complexity of chips driving development costs up, typically into
tens of millions of dollars, people are looking for alternates that can better
leverage those growing investments.
Instead of building optimized hardware dedicated to specific
applications, it has been proposed that programmable devices be used to
mitigate the increased financial and technical risks of delivering application
specific behavior 每 and two different camps supporting this view have emerged.
One faction advocates
abandoning ASICs in favor of FPGAs, ※programmable sea of gates§. A second contingent believes that
modularly scalable and multi-use platforms using multi-core chips is the right
approach 每 and IBM, Intel and others are already shipping such solutions. These
※seas of processors§ have interconnects for communicating between processors
and with external resources. The appeal of multi-cores is based on the ease of
scaling the hardware design and on the fact that, at least theoretically, the
performance is not limited to the capabilities of a single processor, but
scales with the number of processors.
As exemplified by IBM＊s popular Cell Processor for the gaming industry,
multi-cores can also include specialized blocks to enhance performance for a
class of applications. These visions,
were they to become mainstream, promise to end an era of application customized
integrated circuits. Suppose, however, we don＊t
accept that we are destined to follow the current chip development cost
trajectory. I advocate an
alternative vision based on challenging this central assumption. With new methodologies that allow
refinement from high-level models smoothly into hardware (and perhaps even
software) and deliver dramatically better re-use of IP blocks, we can easily
capture desired functionality and have a reasonable expectation of ※getting it
right§. By streamlining these
efforts, new methodologies can materially lower development costs, which are
dominated by front-end design and verification activities not mask costs, as
compared to today＊s approaches.
Consequently, this should allow smaller markets to be targeted with more
application optimized hardware 每 and, allow innovation and customization to
continue to rule silicon design.
And those that succeed in following this alternative path will compete
more adroitly with better targeted solutions.
Multi-core
platforms offer clear benefits:
But
there are several issues. First,
the compilation problem remains unsolved.
Without the ability to efficiently abstract the programming of these
devices, they will only have potential performance that will never be
realized. Network processor
experiences illustrate this 每 many use multi-core, programmable architectures
and make tremendous performance claims, until one uses them in practice. While in some cases it may be possible
to meet specifications with hand-tuned assembly code, the resulting development
process is too long and prone to error.
Second, with multi-core platforms, power and performance estimation is
all but impossible without completing development, as too many implementation
decisions have first-order impacts, e.g. mapping of application across the
cores; firmware on the cores; and memory, switch and interconnect dynamics and
utilizations. Finally, for many markets, such as mobile, the low energy
requirements cannot be met with multi-core architectures without a significant
investment in specialized blocks. An Alternative
Vision: HW Innovation through Refinement and Re-Use The rumors of hardware
innovation＊s demise are premature.
My research has focused on changing the current assumptions driving chip
development costs. Instead of
Verilog, which has its roots in modeling and simulation, and not in synthesis,
and has weak semantics for scaling designs, interconnecting modules, promoting
re-use and managing concurrency, I am focused on a new methodology that allows
designers to assemble system-on-chips and ASICs quickly and accurately. More often, designers should use
pre-existing, application-optimized IP, better parameterized and correctly
instantiated, by construction. And
when new IP needs to be created, new functionality can be developed correctly
and rapidly, enabled by better semantics for managing complex concurrency and
design composition. Add refinement
from transaction to implementation-level within the same environment and
architectural assessments can be based on actual implementation costs and
development can be significantly more efficient. These approaches can be leveraged for both FPGAs and ASICs. While the differences in power,
performance and cost between the two technologies won＊t change, the risk
differential will diminish. The
benefits of designing with this new methodology can be quite dramatic. In an advanced hardware design course
taught this past spring at MIT, 6.884 (http://csg.csail.mit.edu/6.884/), we
used Bluespec, a high-level design environment based on guarded atomic actions,
for rapid IP implementation and architectural exploration. The students＊ projects, which included
architecture specification, verification, implementation, architectural
exploration studies, and physical layout and device characterization, were
completed in only six weeks after just a six-week training with some laboratory
exercises. All together there were six different project teams and examples of
what they completed in such a short timeframe included: ﹞
An out-of-order SMIPS processor using Tomasulo＊s
algorithm ﹞
An 802.11a transmitter We expect to do much more
this term, especially in terms of packaging IP for future use in projects. The
goal is show that complex, customizable designs can be cost effective to
develop, allowing semiconductor manufacturers to attack smaller markets with
more targeted solutions.
Acer Executive Column - Me Too Is Not My Style (Part IX)
Brian Bailey＊s Column 每 Performance Is a Big Deal
Addison Wisley Featured Book Column 每 Planning a Warehouse Inventory System
Morgan Kaufmann＊s Featured Book Chapter Column 每 Networks on Chip
Analog Devices Column 每 Design Your Own VoIP Solution with a Blackfin Processor
Software Project Management in Practice 每 Managing Software Projects - India Institute of Technology
TransEDA Column 每 Verification Methodology Manual (Chapter 11)