GUEST EDITORIAL

 

Toward the Jumping Off Point

¨C SoC Design at 65 nm

 

Gary Smith

 

Chief EDA Analyst, Gartner Dataquest

 

 

Talking About SoC Design

There is a lot of talk today about slowing the advance of design technology, and by that I mean slowing that advance on purpose. The example often given is the discontinuation of clock cycle as a measurement of microprocessor performance. Now that we are seeing slower processors being introduced why can¡¯t we just stay at 130 nm or 90 nm processes and save ourselves from the perils of ¡°sliding down the razor¡¯s edge of technology¡±, as it once was described. As is too often true, the microprocessor analogy is actually only half of the story. What we are doing is trading off clock speed and gates. We are using more gates to build parallel systems that perform the same tasks at a lower speed.  This has been a classic design trade off since the beginning of time.  So why can¡¯t we stay at 90 nm? Well speed is basically free, it comes with the process. It takes good designers and more than a few design tricks to do high speed design, but once done the die doesn¡¯t cost you much more that the same function at a slower clock cycle. When you start using parallelism to achieve the same functionality at a lower clock cycle you start eating up gates. That of course causes your die size to grow and that drives up your die cost. The answer is to move to the next process node because the gates are cheaper. Sure you can stay were you are, but if your competition makes the move you get priced out of the market. Technology doesn¡¯t let you sit still for very long.

The Impact of 65 nm Design

There also has been a lot of talk about the horrors awaiting those designers that venture out into the unknown world of 65 nm design. It ends up that it isn¡¯t all that bad. The key issue is that you need to have manufacturing aware EDA Tools and there is a whole lot of processing done after the GDS II tape out. So it ends up what you are really facing are more business questions not design questions. The reality is that the semiconductor design world is starting to look much more like it did in the 1980s than it did in the 1990s. That¡¯s because the 1990s turned out to be the Cream Puff decade. Nothing was really too hard. The silicon was plain old vanilla CMOS, the design methodology was RTL and the challenges were incrementally not that difficult. This allowed the Disaggregation of the semiconductor design chain. A lot of the world went Fabless, design services became popular and the concept of a vertical company was look on as old fashioned, at best.  What we are seeing today Gartner Dataquest calls Competitive Re-Aggregation, the challenge for this decade.

Today¡¯s ASIC Design Challenges

In the beginning of the 1990s we had 100,000 gates to play with; today we have 100 million gates.  That meant that in the beginning of the 1990s we were designing components for a system; today we are designing the system itself (the SoC).  That makes a lot of difference on how you look at your design.  Trying to design a system today using a RTL methodology is like trying to build the pyramids using pebbles.  Today we start at the ES, or Electronic System, Level.  That takes a designer that is as comfortable with embedded software design as he/she is with hardware design. 

In the late 1990s we were told that with a well integrated concurrent design platform, the IC Implementation Tool Set, we no longer needed back end designers. The Design Engineer would tape out the design his/her self.  You then would ship off your design to a foundry using the well hyped COT business model. Do that at 90 nm and you¡¯re dead meat.  Now you can ship off your 90 nm design accompanied by an army of process and product engineers and you would have a good chance of your design working.  At 65 nm even that won¡¯t work. Now the foundry needs to give you some exceptionally sensitive process data before your process and product engineers will even have a chance of getting your 65 nm COT design working.  This of course is where the Competitive Re-Aggregation comes in. The Semiconductor Design Pyramid

For those of you not familiar with the various semiconductor design capabilities, we need to introduce you to the Semiconductor Design Pyramid. This outlines the four different technical/business approaches to using ASIC or Custom silicon in your system design.

The Power Users are at the top of the pyramid. They consists of the top semiconductor design talent. Their organization includes a well staffed internal CAD group and this group develops their own In-House tools to supplement the commercial EDA tools. They design the biggest, the fastest and the most sophisticated ICs in the world.  These are the pros.

The Upper Mainstream is more conservative in their design work. They have a internal CAD group, however they are far less inclined to developed their own In-House tools. They tend to be two to four years behind the Power Users in design capability.

The Lower Mainstream are primarily FPGA designers. They do not have a CAD group and the design engineers are responsible for developing their own scripts and shells needed to put together a design flow. The amount of money spent on EDA tools is an order of

magnitude less than the Upper Mainstream designers.

The Late Adopters seldom design their own ICs and when they do they are usually low end designs using silicon that is three or four generations behind the state-of-the-art.  The EDA tools that they use are inexpensive tools targeted towards academia or freeware.  This group has the nickname of the Cheap Seats.

Today¡¯s SoC Design Chain Business Challenges

Today electronic manufacturers have to reevaluate their design position; just as Semiconductor vendors had to reevaluate having a fab in the 1990s.  Even the Power Users are reevaluating their design flow.  What is on the table for them is the COT issue.  Can they go back to the ASIC model they used in the 1980s and still produce competitive designs.  Let¡¯s face it the competitive advantage in system design comes from the ES Level trade-offs.  Now you do get a far more efficient design by doing your own RTL implementation, but with the amount of DFM work being done after tape out you are gaining less and less by doing your own back end work.  The ASIC model is looking more and more attractive for most Power User designs. 

For the Upper Mainstream companies the decision is even more frightening.  Many of them need to look at whether or not they stay in the design business.  If they do they then need to determine if just doing the ESL design and then handing that off to an ASIC house (the RTL hand-off) will give them the performance they need.  We are actually seeing many companies, especially in the military market, upgrading their design groups to Power User status.  That takes a significant increase in money and resources.  On the other hand we are seeing some companies drop down to Lower Mainstream design, that is disbanding their CAD Team and primarily using FPGA for their designs. 

It¡¯s a tough decision, one of those make or break decisions presidents hate to make.  We had one Power User decide to drop to an Upper Mainstream status and started doing RTL hand-off.  That allowed them to lay off a lot of their designers.  That did two things.  The good news was that they saved a lot of money.  The bad news was that the ICs that they got back were uncompetitive in their market.  Fortunately they were in an area where they were able to hire back most of their design team.  They are now back to being a Power User.  If they had been in Silicon Valley they probably wouldn¡¯t be in business today.