GUEST EDITORIAL

Electronic Design in the 21^st Century

 

Walden C. Rhines

Chairman and CEO

Mentor Graphics Corporation

Ever smaller circuit geometries have enabled designs to evolve from single- or multi-block functional units into whole systems targeted at complex applications in the wireless, consumer, computing, and industrial areas.  According to industry analysts, this trend will only continue, with gate widths of 32 nanometers with 100 billion transistors on a die by 2010.  These systems will not only support digital and analog circuitry, but radio frequency (RF) as well for wireless communications.

As geometries shrink, however, a crop of new issues are arising, challenging design teams.  For example, dealing with complex systems on a chip is leading to design and verification overload, pushing development costs up significantly.  Then, there are the numerous deep submicron effects due to device physics¡ªsuch as static current leakage and timing closure¡ªcomplicating the design task and limiting manufacturing yields.  Designers also need to consider power issues, as passive power starts approximating or even exceeding active power, threatening most applications¡¯ power and thermal budgets.

Fortunately, promising new technologies for designers are coming to market, targeted at the areas of most intense pressure for today¡¯s design teams in physical design, verification and front-end design. 

Improving yield

Until recently, designers did not have to deal much with back-end physical design issues.  As long as they adhered to the rule decks from the manufacturer, all was well.  But now back-end physical design is demanding more attention from designers in the nanometer realm.  Sub-wavelength lithography processes introduce new yield loss mechanisms leading to an increase in defects per million rates.   It is not enough to follow the rules.  Instead complex tradeoffs need to be made in design, requiring a closer relationship between design and manufacturing.

Looking for ways to enhance yield outcome, designers are relying on new technologies that allow them to optimize for manufacturing at each stage of the design, verification, tapeout and test process. One of the most fundamental changes is the integration of design for manufacturing (DFM) with design for test flows, especially in closing the loop between manufacturing and design. Analysis of test data from manufacturing test creates a true goldmine of information for calibrating today¡¯s largely qualitative DFM rules and computing yield sensitivity functions.

Easing the verification overload

As more gates are included on ICs, verification is consuming an ever larger portion of a design team¡¯s time and resources.  A recent study shows that 49 percent of design engineering time is focused on verification.  Increasing complexity will only exacerbate the problem.  In response, design teams are adopting a host of new methodologies¡ªassertion-based verification, coverage-driven verification, and widespread use of automatic testbenches.

Using assertion-based verification (ABV), verification engineers can more effectively test a design to ensure the design matches its functional specification. When combined with functional coverage capabilities in a scalable verification environment¡ªsuch as the new generation of System Verilog verification products just now coming to market¡ªengineers finally have a means to track the effectiveness of their verification efforts. The result is coverage-driven verification, in which designers use feedback from testing to target their successive tests, resulting in greatly improved productivity and effectiveness.

Built around standard, multi-vendor supported languages, these tools offer designers a methodology for easily implementing a 'golden source' from the algorithmic level of abstraction down to technology-specific RTL.  This significantly streamlines the verification effort, eliminating the need to re-create the testbench at the HDL and hardware level

Abstracting up a level in design

During front-end design, performance, power and cost issues all need to be carefully balanced to eliminate costly redesigns on the backend. Designers need a method for evaluating competing architectures to arrive at the optimal approach.  However, the traditional method of synthesizing from RTL is too time-consuming and cumbersome to allow for wide-ranging architectural exploration. New tools raise the level of abstraction for front-end design, delivering on the promise of ESL for design, synthesis, and verification.  Based on the simulation and synthesis of C representations, hardware engineers can now design, automatically synthesize and verify hardware, leveraging the same untimed C++ source typically generated by system designers.  The ability to work at a far more productive abstraction level frees the design team to explore architectural tradeoffs and fine-tune designs for desired size, power and performance metrics. 

Moving Forward

Raising the level of design abstraction, streamlining verification and improving yield with advanced DFM and test strategies should go a long way towards keeping IC design on track.  Using these techniques, design teams can continue to produce ever more complex ICs while keeping within time and cost budgets. New advancements across the entire design continuum will enable electronic design to continue to thrive in the 21^st century, even as gate counts climb into the millions and IC geometries continue to shrink.