GUEST EDITORIAL

 

What Must Be Solved Quickly in System-Level Design Supports?

 

Professor Masahiro Fujita

VLSI Design and Education Center, The University of Tokyo

 

ystem LSI designs include not only hardware LSI chip designs but also developing software that runs on top of the hardware. They are extremely complicated/large systems and can be reasonably well analyzed only in very abstracted design levels. This suggests that it is time to seriously consider various uses of CAD techniques for designs higher than RTL (Register Transfer Level). There are, however, a couple of obstacles for actual uses of them:

(1)  Synthesis from higher level design descriptions must be inevitable, but synthesis tools from behavior or higher may not be ready yet

(2)  Clearly simulation/emulation is not sufficient for large complicated designs, but formal verification techniques are not yet used much.

(3)  Synthesis tools may not be so robust especially in the introductory phases, and so the verification of the correctness of the synthesized designs is a must. Unfortunately, equivalence checking tools between behavior and RTL are not yet available.

These are the issues to be solved very quickly in order to smoothly support high level designs for system LSI. In the followings the backgrounds and the problems relating to these issues are discussed in order.

First of all, it is very essential to apply high-level synthesis (or behavior synthesis) in real design environments in order to obtain much higher productivity of system LSI designs. High-level synthesis techniques have been intensively researched, and various tools have been developed for the past 30 years or so. The history of high level synthesis may be the same as logic synthesis which has been actually used in real design environments for more than 10 years. Why are logic synthesis tools used but not high level synthesis tools? With the state-of-the-art technology, both can work on ˇ°moduleˇ± or ˇ°blockˇ± level designs. Each block which has 10K ~ 100K gates may be automatically synthesized. In that sense, high level synthesis tools should be able to be used in principle, but the reality is not. The reason is the fact that logic synthesis does not change ˇ°scheduling of operations/computations, but high level synthesis does change a lot. Change of scheduling can influence on exact timings of communication with other blocks or modules. This means we cannot synthesize each block ˇ°independentlyˇ±, since communication with other blocks must well be taken into account. Unfortunately current high level synthesis tools can process each block one by one but cannot deal with multiple blocks simultaneously due to extremely large complexity in analyzing multiple concurrent activities. Since this is essentially the same problem that can be found when applying formal verification techniques to real life designs, the second problem is discussed next.

Everyone agrees that due to extremely large complexity of system LSI designs, formal verification techniques should be applied besides simulation/emulation. But so far very limited formal verification techniques have been introduced into real design environments. The reason is simply the applicability of formal verification tools. They can never be used for large designs as they are, due to so called ˇ°state explosionˇ± problems. Numbers of states (or state combinations) to be analyzed will increase exponentially with numbers of concurrent processes in the designs. So this is exactly the same problem that we discussed on high level synthesis tools. Formal verification research community has been intensively working on ˇ°abstractionˇ± of designs for verification. This technique tries to reduce numbers of states to be analyzed significantly by merging multiple states into one still keeping the correctness of formal verification. Same or similar techniques should be able to be applied also to high level synthesis of multiple concurrent blocks. Although this technique is mostly in research phase, there have been reported already many applications to real designs. So the issue is how to introduce ˇ°abstractionˇ± techniques into real design flows for system LSI designs.

Now we discuss about the third topic. Equivalence checking between two gate level net lists or RTL is now becoming very common. This technique works very well if the two designs to be compared are reasonably ˇ°similarˇ±. However, behavior design descriptions which are inputs of high level synthesis tools and RTL design descriptions which are outputs are completely different. Scheduling and types of operations may be drastically change through high level synthesis. But the actual problem in equivalence checking between behavior and RTL descriptions is how to ˇ°defineˇ± the equivalence. Designers only know details of behaviors design descriptions, but do not understand at all the synthesized RTL descriptions, since they are automatically generated by the synthesis tools. Therefore, it is not easy for designers to make sure the correctness of the synthesized designs. Since high level synthesis is a complicated process, synthesis tools should be used with verification tools that can make sure the correctness of the synthesized designs. We need systematic methods by which designers can understand the synthesized RTL descriptions and define the equivalence. So far there are only very limited work on this problem, but this is an essential problem which must be resolved before high level synthesis tools are widely introduced.