From ASIC Design to Structured ASIC Design
From C/C++ to Synthesizable Verilog/SystemVerilog
Advanced Physical Synthesis in COT Flow
Advanced Perl for ASIC/SoC Design
Automatice Testbench Generation in Verilog
System Modeling & Verification with C++/C
Advanced Synthesizable VHDL at RTL in Depth
Migrating from ASIC Design to IP-based SoC Design
From Algorithm to RTL in Synthesizable Verilog
Negotiating & Drafting High-Tech Business Agreement
Migrating from ASIC Flow to COT Flow
Low Power Design Techniques for High Performance CMOS IC
Key Issues in Reliable High Speed PCB Design
Issues in Designing Mixed-Signal Design
HW/SW Co-Design for SoC in SystemC
HW/SW Co-Design & Co-Simulation for Platform-based SoC
FPGA based Custom Prototyping in Accelerating Your SOC Design
EDA Flow (IC Design Process) Setup & Turning
ASIC/SoC Modeling, Synthesis & Verification from C
Advanced Verification/Validation Techniques
Advanced Synthesizable VHDL at RTL in Depth
Advanced Symposium on IP based SoC Integration
Static Timing Analysis & Optimization Techniques
Advanced RTL Design - From Algorithm to System
Synthesis for Timing Closure & Signal Integrity
Advanced High Performance RTL Design From Algorithm
Technical Aspects of IC Project Management
ATPG, DFT & BIST for ASIC/SoC
Timing-driven Logic Synthesis for IP-based SoC Design
Very/Ultra Deep Sub-Micron (VDSM) Issues in SoC Design
© Copyright 2002-2008 Hometown Innovation Automation Inc
All Rights Reserved
Back to Home Page
